CIF: Imperfection-Resilient Scalable Digital Signal Processing Algorithms and Architectures Using Significance Driven Computation

CIF：使用重要性驱动计算的不完美弹性可扩展数字信号处理算法和架构

• 批准号: 0916270
• 负责人: Abhijit Chatterjee
• 金额: $ 25万
• 依托单位: Georgia Tech Research Corporation
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 2009
• 资助国家: 美国
• 起止时间: 2009-07-15 至 2013-06-30
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=0916270&HistoricalAwards=false
• 关键词: CIF; Imperfection; Resilient; Scalable; Digital

Present-day integrated circuits are expected to deliver high-quality/high-performance levels under ever-diminishing power budgets. Due to quadratic dependence of power on voltage, supply voltage scaling has been investigated as an effective method to reduce power. However, supply scaling increases the delays in all computation paths and can result in incorrect or incomplete computation of certain paths. Besides power dissipation, process variations also pose a major design concern with technology scaling. Supply voltage can be scaled-up or logic gates can be up-sized to prevent delay failures and to achieve higher parametric yield. However, such techniques come at the cost of increased power and/or die area. Meeting the contradictory requirements of high yield, low power and high quality are becoming exceedingly challenging in nanometer designs. Hence, there is a need for a scalable design methodology in which minimal output quality degradation is achieved under changing power constraints and process conditions. In addition, for a prescribed power consumption level and process, design methodology must take into account the effects of input signal noise and distortion on the fidelity of the Digital Signal Processing (DSP) computation and ensure that graceful output quality degradation is achieved under varying degrees of noise and distortion through proper algorithm and hardware design. The research involves development of a systematic methodology for reorganizing (transforming) algorithmic level computations, data and underlying hardware in such a way that minimum performance degradation in DSP systems is achieved under reduced power supply, increased process variations and reduced input signal quality. It has been observed that for DSP applications/systems, all computations are not equally important in shaping the output response. This information is exploited by the investigators to develop suitable algorithms/architectures that provide the ?right? trade-offs between output quality vs. energy consumption (supply scaling) vs. parametric yield due to process variations vs. input signal noise. To address resilience to process variations, the investigators identify the significant/not-so-significant components of such systems based on output sensitivities. Under such a scenario, with scaled supply voltage and/or parameter variations, if there are potential delay failures in some paths, only the less-significant computations are affected. In other words, using carefully designed algorithms and architectures, the investigators provide unequal error protection (under voltage over-scaling) to significant/not-so-significant computation elements, thereby achieving large improvements in power dissipation with graceful degradation in output signal quality.

当今的集成电路有望在不断减少的功耗预算下提供高质量/高性能水平。由于功率与电压的二次相关性，电源电压缩放已被研究为降低功率的有效方法。然而，电源缩放会增加所有计算路径中的延迟，并可能导致某些路径的计算不正确或不完整。除了功耗之外，工艺变化也是技术扩展的主要设计问题。可以按比例放大电源电压或增大逻辑门的尺寸，以防止延迟故障并实现更高的参数良率。然而，此类技术的代价是增加功率和/或芯片面积。在纳米设计中，满足高产量、低功耗和高质量的矛盾要求正变得极具挑战性。因此，需要一种可扩展的设计方法，在不断变化的功率限制和工艺条件下实现最小的输出质量下降。此外，对于规定的功耗水平和流程，设计方法必须考虑输入信号噪声和失真对数字信号处理（DSP）计算保真度的影响，并确保在不同程度上实现输出质量的适度下降。通过适当的算法和硬件设计来消除噪声和失真。 该研究涉及开发一种系统方法，用于重组（转换）算法级计算、数据和底层硬件，从而在电源减少、工艺变化增加和输入信号质量降低的情况下实现 DSP 系统性能下降最小化。据观察，对于 DSP 应用/系统，所有计算在塑造输出响应方面并非同等重要。研究人员利用这些信息来开发合适的算法/架构，以提供“权利”。由于工艺变化与输入信号噪声而导致的输出质量与能耗（电源缩放）与参数良率之间的权衡。为了解决过程变化的弹性问题，研究人员根据输出敏感性识别此类系统的重要/不那么重要的组件。在这种情况下，随着电源电压和/或参数变化的变化，如果某些路径中存在潜在的延迟故障，则仅影响不太重要的计算。换句话说，利用精心设计的算法和架构，研究人员为重要/不那么重要的计算元件提供不等错误保护（欠压过缩放），从而实现功耗的大幅改善，同时输出信号质量适度下降。