Investigation of Reliability-Constrained On-Chip Networks

可靠性受限片上网络的研究

• 批准号: 0541417
• 负责人: Timothy Pinkston
• 金额: $ 37.5万
• 依托单位: University of Southern California
• 依托单位国家: 美国
• 项目类别: Continuing Grant
• 财政年份: 2006
• 资助国家: 美国
• 起止时间: 2006-04-15 至 2012-03-31
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=0541417&HistoricalAwards=false
• 关键词: Investigation; Reliability; Constrained; Chip; Networks

Abstract0541417Alexander SawchukLos Angeles, CAInvestigation of Reliability - Constrained On-Chip NetworksAmong the many challenges computer architects will face over the next decade and beyond is the growing demand for reliable on-chip communication between system microarchitecture functional domains. Continued increases in scaling and integration of transistor and wiring resources are allowing more system functions to be implemented on chip, but also more circuit defects and variability. Recent trends toward partitioning the system microarchitecture into multiple on-chip compute domains in the form of functional unit blocks, tiles and processor cores mitigate chipcrossing delays and facilitate chip survivability. That is, it helps to prevent system performance and cost from being encumbered by deep submicron technology scaling. With these developments, support for low latency, high throughput, and fault tolerant communication is becoming more and more critical within the on-chip network used to interconnect the compute domains. Much recent research is directed toward the design of on-chip networks to meet certain cost/performance goals(chip area, latency and throughput), but very little architecture research explores on-chip networkreliability issues specific to the problem of hard faults, which is recognized as a growing problem.In this research, we investigate reliability challenges and techniques for on-chip networks that will meet manufacturing yield and chip reliability targets as technology scales into the deep submicron regime. The goal is to understand the problem more fully and to develop on-chip network techniques for efficient resource and reliability management, fault isolation, dynamic reconfiguration and fault recovery to allow fault-stricken microarchitectures partitioned across a chip to have increased usability and prolonged life. We endeavor to increase understanding of chip failure mechanisms (their causes and impact); appropriately model them as related specifically to on-chip networks; develop approaches and techniques that will allow on-chip networks (in cooperation with techniques for other components of the chip microarchitecture) to be resilient tohard faults; evaluate and assess the benefit of the proposed techniques under expected workloads and common-case operational conditions; and, furthermore, understand the tradeoffs in using the proposed fault-resilient on-chip network techniques that is, identify those situations in which various techniques can be most usefully applied given the existence of other possible constraints. The Intellectual Merit of this research is substantial. The research is timely as it addresses an important issue that will only worsen with continuing advancements in technology scaling. The research will culminate with key contributions made in (1) increasing our understanding of the fundamental design, process, and operational mechanisms most responsible for on-chip interconnect failures and (2) producing original and promising techniques for increasing on-chip interconnect reliability and chip reliability as a whole. Beyond the specific results produced by the models and simulation environments we will develop through this project, these tool artifacts will likely have a profound impact on future research infrastructure and education for years to come. Theywill be invaluable assets to researchers, students, and practitioners for understanding, developing,evaluating, and trading-off alternative reliability techniques as demanded by advanced technologies and systems. The tools we develop will be made publicly available and are expected to have widespread use. The results of this research will also be widely disseminated through publications. The Broader Impact of this research is significant and far-reaching. This research can have a profound impact on the success of near-future nanoscale technologies (molecular, quantum, etc.) used to implement integrated circuits beyond the CMOS era as ICs implemented in these technologies are expected to have substantially more hard faults (orders of magnitude) than CMOS ICs. Reliability techniques such as the ones that will be derived from this research will be critical to systems implemented in these technologies as well as those implemented in future deep submicron technology. In the nearer term, many of the ideas coming from this research may be transferrable to system-level networks, where form-factor constraints often are not as rigid as they are on-chip.

Abstract0541417Alexander Sawchuklos Angeles，Cainvestigation的可靠性 - 受约束的芯片网络室，计算机架构师将在未来十年中面临许多挑战，而超越了对可靠的芯片机上微型结构功能域之间可靠的芯片交流的需求。晶体管和接线资源的扩展和集成的缩放和集成允许在芯片上实现更多的系统功能，但电路缺陷和可变性也有更多。将系统微体系结构划分为多个芯片计算域的最新趋势，其功能单位块，瓷砖和处理器核心的形式减轻了芯片延迟并促进芯片生存能力。也就是说，它有助于防止系统性能和成本受到深层次级技术扩展的影响。通过这些发展，在用于互连计算域的片上网络中，对低延迟，高吞吐量和容错通信的支持变得越来越重要。 Much recent research is directed toward the design of on-chip networks to meet certain cost/performance goals(chip area, latency and throughput), but very little architecture research explores on-chip networkreliability issues specific to the problem of hard faults, which is recognized as a growing problem.In this research, we investigate reliability challenges and techniques for on-chip networks that will meet manufacturing yield and chip reliability targets as technology scales into the deep submicron regime.目的是更充分地了解问题，并开发片上网络技术，以有效的资源和可靠性管理，故障隔离，动态重新配置和故障恢复，以允许跨越芯片的故障折磨的微体系结构，以增加可用性并延长寿命。我们努力提高人们对芯片故障机制的理解（它们的原因和影响）；适当地将它们与片网络专门相关；开发方法和技术将允许芯片网络（与芯片微体系结构其他组件的技术合作）是弹性的Tohard故障；在预期的工作量和公共操作条件下评估和评估所提出的技术的好处；此外，在使用所提出的故障固定网络技术的情况下，请理解折衷方案，即确定那些在存在其他可能的约束的情况下，可以最有效地应用各种技术的情况。 这项研究的智力优点是巨大的。这项研究是及时的，因为它解决了一个重要的问题，这只会随着技术扩展的持续进步而恶化。这项研究将以（1）在（1）中提出的关键贡献达到顶峰，以增加对芯片互连失败最负责的基本设计，过程和操作机制的理解，以及（2）产生原始和有希望的技术，以提高芯片互联的可靠性和整体芯片可靠性。除了通过该项目开发的模型和模拟环境产生的具体结果外，这些工具工具可能会对未来几年的未来研究基础设施和教育产生深远的影响。它们将对研究人员，学生和从业者来说是宝贵的资产，以理解，开发，评估和交易替代性可靠性技术，如先进的技术和系统所需的替代可靠性技术。我们开发的工具将公开可用，并有望广泛使用。这项研究的结果还将通过出版物广泛传播。这项研究的更广泛影响是重要的和深远的。这项研究可能会对近未实现的纳米级技术（分子，量子等）的成功产生深远的影响，用于实施CMOS ERA以外的集成电路，因为这些技术在这些技术中实施的IC预计将比CMOS IC具有更大的硬故障（数量级）。可靠性技术诸如将从这项研究中得出的技术对于这些技术中实施的系统以及未来深层次级技术实施的系统至关重要。在近学期中，这项研究的许多想法可能可以转移到系统级网络，在系统级网络中，形式的因素限制通常并不像芯片那样僵化。