CAD Algorithms for Automated, Hierarchical, Bottom-Up Abstraction of Large Digital Aggressor Blocks for Supply and Substrate Noise Analysis

用于自动、分层、自下而上抽象大型数字干扰模块的 CAD 算法，用于电源和基板噪声分析

• 批准号: 0541396
• 负责人: Jaijeet Roychowdhury
• 金额: $ 20万
• 依托单位: University of Minnesota-Twin Cities
• 依托单位国家: 美国
• 项目类别: Continuing Grant
• 财政年份: 2006
• 资助国家: 美国
• 起止时间: 2006-03-01 至 2009-02-28
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=0541396&HistoricalAwards=false
• 关键词: CAD; Algorithms; Automated; Hierarchical; Bottom

ABSTRACT0541396Jaijeet RoychowdhuryU of Minnesota- Twin CitiesCAD Algorithms for Automated, Hierarchical, Bottom-Up Abstraction of Large Digital Agressor Blocks for Supply and Substrate Noise AnalysisToday, virtually every aspect of our technological society today relies on a variety of digital and mixed-signal integrated circuits (ICs), which are growing larger and more complex by the day. To continue to design such chips effectively, estimating the interference noise generated by large numbers of switching digital blocks has become exceedingly important. Increasing levels of current drawn, higher switching speeds (clock frequencies) and falling supply voltages in new technologies conspire to worsen levels of interference noise and to exacerbate its debilitating impact on system functionality and performance. Interference noise that has not been correctly estimated and contained leads to failed production runs, delays in design turnaround,increased development costs and longer times to market. In this project, algorithms, methodologies and prototype CAD tools for predicting digital interference noise will be developed. The core of the project is to develop algorithms to extract accurate -- yet computationally-inexpensive -- noise macromodels of large blocks of digital aggressors. The resulting noisemacromodels will be used to develop a methodology for fast prediction of on-chip interference noise via both power-grid and substrate-coupling mechanisms. Unlike prior attempts, the project unified the prediction of interference noise digital design (e.g., switching noise margin, power/ground bounce induced delay variations) and for mixed-signal/analog/RF design (e.g., interference-induced spurs, SNR degradation and PLL jitter). Because the approach is algorithmically-based and not tied to any particular technology or design style, it is also easily adapted to apply nanoscale devices and mixed-domain systems containing electronics, optics, and MEMS. Thus, the project is expected to have significant broad impact in the general arena of high-performance hardware for communication, computational and sensor systems. The algorithms developed will be disseminated as open-source code, further accelerating and enhancing the project's impact in the technological community.

摘要0541396JAIJEET ROYCHOWDHURYU的twin twin Codcad算法用于自动化，分层，自下而上的大型数字隔离器块，用于供应和基板噪声分析的供应和基板噪声分析，这实际上是我们的技术社会的每个方面，这些方面实际上是在各种数字和混合循环的综合循环（ICLECT）的综合循环（IC），这是综合循环的（IC）。为了继续有效地设计此类芯片，估计大量开关数字块产生的干扰噪声变得非常重要。 新技术中的电流绘制水平，更高的开关速度（时钟频率）和供应电压下降，使干扰噪声的水平恶化，并使其对系统功能和性能的影响衰弱。 尚未正确估计并包含的干扰噪声导致生产失败，设计周转延迟，开发成本增加以及更长的市场时间。在此项目中，将开发用于预测数字干扰噪声的算法，方法和原型CAD工具。该项目的核心是开发算法，以提取大型数字侵略者块的准确（但计算中的）噪声大型模型。由此产生的噪声模型将用于开发一种方法，以通过电网和底物耦合机制快速预测芯片干扰噪声。与先前的尝试不同，该项目统一了干扰噪声数字设计的预测（例如，开关噪声余量，电源/接地弹跳诱导的延迟变化）和混合信号/模拟/RF设计（例如，干扰诱导的刺激器，SNR降解和PLL抖动）。 由于该方法是基于算法的，并且与任何特定的技术或设计样式均不链接，因此它也很容易适应纳米级设备和包含电子，光学和MEMS的混合域系统。因此，预计该项目将在通信，计算和传感器系统的高性能硬件的一般舞台上产生重大影响。 开发的算法将作为开源法规传播，进一步加速和增强项目对技术界的影响。