高温SiC DMOS器件电热物理场耦合模型与加固新结构研究

This project is aimed at the thermal stress related reliability issues in SiC power DMOS for the high temperature application, committed to two theoretical and experimental creative research topics: 1. To propose a three-dimensional coupled electro-thermal modeling of SiC DMOS, exploring the inner functional relationship of the junction temperature, physical structure, dimensions and bias conditions. If the variation of the thermal conductivity of SiC is taken into account, the 3D heat diffusion equation becomes nonlinear and an explicit steady state analytical expression can be found using a double Kirchhoff transform. Meanwhile, an accurate estimation and fast analysis method for transient heat conduction problems can be developed by the proper orthogonal decomposition (POD). 2. To understand the performance degradation and failure mode or mechanism under UIS condition，the avalanche currents and hot-carrier generation and transport mechanism to the SiC DMOS for operation at high temperature are discussed in detail. A novel SiC DMOS with the patterned gate structure by using a split path of avalanche current technology is proposed. Based on the idea of the avalanche current path modulation, the location and magnitude of the voltage breakdown of SiC DMOS will be changed from Pbase/N- junction to P+/N- junction using the recessed P+ structure in the source region, resulting in the decrease of UIS failure triggered by large peak avalanche currents caused by parasitic BJT latch-up. Furthermore, the patterned gate structure is employed to modulate the drain current density distribution of SiC DMOS, preventing the formation of a hot-spot and device failure, thus resulting in the improvement of thermal reliability. This project is a fundamental application research about the physics and methods of thermal reliability of devices and it will provide accurate thermal design and afford an effective way to improve the performance of the high-power SiC DMOS devices.

本课题针对大功率SiC DMOS器件高温工作中热效应严重退化器件功率处理能力的问题，进行一个模型和一种新结构的创新研究：(1) 通过考虑材料热导率随温度的变化，采用双基尔霍夫变换方法和特征正交分解法建立SiC DMOS器件电热耦合物理场分析模型，探索器件多物理场耦合环境下的行为特征，揭示器件物理结构尺寸、偏置条件对稳态和瞬态温度场分布的作用规律，快速准确地预测出器件热点形成位置。(2) 探讨高温下器件雪崩电流和热载流子产生与输运机制，阐明器件动态雪崩性能退化及烧毁的失效模式与机理，提出一种基于雪崩电流路径分离技术的图形化栅极新结构。采用凹陷P+源极结构来调制雪崩电流路径，避免寄生晶体管开启导致的热失效；同时采用图形化栅极结构，调节芯片元胞电流密度分布，避免出现局部过热而烧毁。本课题是一项器件热可靠性物理与加固方法的应用基础研究，将为SiC DMOS器件的高温应用提供一种新的设计与加固思路。

宽禁带半导体碳化硅（SiC）材料具有宽带隙、高临界击穿电场、高热导率、高电子饱和漂移速度等突出优点，与传统硅基功率器件相比，SiC功率器件可将装置功耗和体积降低一半以上，正逐步应用于混合动力/电动汽车、光伏/风力发电、高铁牵引设备、特高压直流输电等新兴能源领域。大功率SiC器件已成为当前国际上功率器件领域的研究热点和重要发展方向之一，具有极其重要的民用和军用价值，是各国竞相抢占的能源战略制高点。然而，高功率密度SiC MOSFET器件的电热可靠性一直是制约其工程化应用的最大障碍，也是其迈向实用化的关键瓶颈问题，亟待在器件电热耦合物理场分析模型、雪崩失效机理及其加固结构等方面获得突破。.本项目从SiC MOSFET器件物理本质出发，① 根据器件热效应机理，建立了电特性和热特性相互影响的多物理场耦合分析模型，获得了不同功率条件下的器件温度场分布，明确了电学和热场分布的相互影响关系，为评估器件实际工作中的温度分布提供了一种快速且准确的方法。② 通过研究非钳位感性负载开关雪崩过程中SiC MOSFET器件载流子的输运机理，探索了器件动态雪崩性能退化及烧毁的失效机理。考虑国内现有SiC制造工艺技术，基于雪崩电流路径分离的思想，提出了一种凹陷P+源极SiC MOSFET结构，使雪崩电流路径从Pbase/N-Drift拐角处转移至P+源极下方，减少了雪崩过程中栅氧化层中热载流子的注入。相较于传统SiC MOSFET结构，凹陷P+源极结构在雪崩击穿时SiC/SiO2界面处碰撞电离率下降了2个数量级，沟道区的温度降低了10℃，显著抑制了热空穴注入栅氧化层而导致的栅氧化层退化现象。③ 开展了3.3kV SiC MOSFET器件的制备与测试分析研究。器件最大击穿电压为3.5kV，导通电阻70mΩ，阈值电压>2V；300μH负载电感下的雪崩峰值电流24A，雪崩时间30μs，雪崩能量0.09J；3.6mH负载电感下的雪崩峰值电流15A，雪崩时间50μs，雪崩能量0.41J；初步验证了3.3kV SiC MOSFET器件的UIS可靠性。.本项目获得的热分析模型、器件加固结构、器件制备等研究成果对改善和提高SiC MOSFET热相关可靠性，加快其在新能源领域的实用化进程具有一定的指导和借鉴意义。

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