基于双极性自选通忆阻器的非易失可重构逻辑原理与实现研究

Memristive nonvolatile stateful logic can realize the unity of information storage and processing and is regarded as a disruptive technology to break the von Neumann bottleneck in traditional computing architecture in the post Moore's era. This project will develop bipolar self-selective memristors which is quite promising in future high density three-dimensional integration. First we will try to reveal the physical mechanisms responsible for the nonlinear electrical transport behaviors and the resistive switching behaviors. Second, we will develop functionally complete nonvolatile Boolean logic methodologies based on the practical I-V behaviors of the memristors. Third, we will propose the reconfigurable logic methods in the crossbar array and realize the complex computing tasks in a parallel and energy-efficient manner. The influence of the device parameters such as nonlinearity, uniformity, resistance window, switch speed and power consumption on the correctness and efficiency of computing will be analyzed carefully. The possible mis-read and mis-write problems brought by the leakage current, parasitic capacitance and line resistance will also be addressed in our study. This work will make breakthrough in high-performance self-selective memristors, nonvolatile stateful logic principles and reconfigurable logic in array, which will lay a solid foundation for the construction of non von Neumann computing architecture and systems. Our research will have important scientific influence and practical application value.

忆阻非易失逻辑可以融合存储与计算功能，是后摩尔时代突破传统冯·诺依曼计算架构的颠覆性存算一体技术候选。本项目拟研制在高密度三维集成中具有优势的双极性自选通忆阻器，深入阐明器件的非线性传输特性和电阻转变特性的物理机制，重点针对自选通器件特性发展完备非易失布尔逻辑原理，提出交叉阵列中逻辑功能的可重构实现方案，以高效并行实现复杂运算功能，全面分析非线性度、一致性、阻变窗口、开关速度、功耗等器件参数对逻辑运算可靠性及效率的影响，解决阵列中并行计算时由漏电流通路、寄生电容效应、线电阻导致的误读、误写等误操作问题。本项目将在高性能自整流忆阻逻辑器件、非易失性状态逻辑运算原理、忆阻阵列可重构逻辑实现方法等方面取得原始创新和突破，为构建非冯·诺依曼计算架构和系统奠定基础，具有重要的科学意义和应用价值。

发展高性能自选通忆阻器是实现低功耗非易失可重构逻辑的重要途径，是构建高能效存内计算系统的重要候选技术。本项目重点在自选通忆阻器及可重构逻辑等存内计算方案设计领域开展系统探索，系统性地提出了界面工程、能带工程、缺陷浓度调控等自选通忆阻器性能调控方法及工艺，研制出氧化铝基自选通忆阻器和氧化钽基自整流忆阻器，在速度、擦写次数、一致性、功耗、可扩展能力等指标方面获得突破；提出了基于自选通忆阻器的非易失布尔逻辑方案，实现运算单元数、操作步数的优化；研究了基于自整流忆阻器阵列的复杂可重构逻辑方案设计原理，并实现了多种复杂逻辑功能；研究了钒基自选通忆阻器在全忆阻脉冲神经网络、TCAM存内搜索等新兴领域的应用潜力；探索了基于自整流忆阻器阵列的矩阵运算范式，搭建了基于自整流忆阻器阵列的高性能存内计算系统。研究成果共发表论文24篇，其中国际期刊论文20篇，国际会议论文4篇；培养博士生6人，硕士生5人；申请发明专利16项，其中已授权6项；与华为公司合作开展忆阻存内搜索技术的研究。

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