Design for Testability and Hardware Security

可测试性和硬件安全性设计

• 批准号: RGPIN-2017-04926
• 负责人: Rashidzadeh, Rashid
• 金额: $ 1.75万
• 依托单位: University of Windsor
• 依托单位国家: 加拿大
• 项目类别: Discovery Grants Program - Individual
• 财政年份: 2020
• 资助国家: 加拿大
• 起止时间: 2020-01-01 至 2021-12-31
• 项目状态: 已结题
• 来源: https://www.nserc-crsng.gc.ca/ase-oro/Details-Detailles_eng.asp?id=711299
• 关键词: Design; Testability; Hardware; Security

The new generation of integrated circuits include high performance analog and digital blocks, processing units, memories, and sensors. While such new microchips provide opportunities to enhance the performance of portable devices significantly, they also pose new challenges. Developing manufacturing tests for advanced integrated circuits while ensuring their hardware security is a formidable task. A great deal of progress has been made in developing various test methodologies for microchips. Efficient Design-for-Testability (DFT) techniques such as scan and Built-in Self-Test (BIST) are widely used to carry out tests on digital circuits. However, the DFT methodologies have been developed without adequate attention to security implications. For instance scan-chain insertion, one of the most effective DFT techniques, can be utilized to access the critical information inside a chip. The requirements for testability and hardware security are in sharp contrast with one another. To test a chip, access to the internal circuits are needed to apply test vectors to desired sub-circuits and observe their responses. While such full access is considered ideal for manufacturing tests, it is clear that such unrestricted access to the internal circuits of a device can undermine its security. For decades, hardware was assumed to be the source of trust-and-security but this assumption is not true anymore due to outsourcing. The costs of a fabrication line are so high that only a few companies can afford to have an in-house fabrication line. The outsourcing of in-house fabrication to overseas foundries provides opportunities for malicious activities and paves the way for potential security threats known as hardware Trojans. The current solutions for testability have to be modified to detect undesired hardware modifications and prevent security breaches using the test infrastructure. The main objective of this work is to advance the design-for-testability and security techniques for the new generation of integrated circuits to ensure both testability and hardware security while reducing the overall manufacturing costs. The specific aims of this research proposal are to: (a) Develop a Design for Secure Testability Method for 3D ICs using an RFID based Authentication. (b) Implement a Test Technique to Detect Hardware Trojans. (c) Develop a Pre-bond Test Solution for 3D Stacked ICs. (d) Develop a Fault Model for FinFET Based Circuits.

新一代集成电路包括高性能模拟和数字模块、处理单元、存储器和传感器。虽然此类新型微芯片为显着增强便携式设备的性能提供了机会，但它们也带来了新的挑战。为先进集成电路开发制造测试，同时确保其硬件安全是一项艰巨的任务。在开发微芯片的各种测试方法方面已经取得了很大进展。扫描和内置自测试（BIST）等高效的可测试性设计（DFT）技术被广泛用于对数字电路进行测试。然而，DFT 方法的开发并没有充分关注安全影响。例如，扫描链插入是最有效的 DFT 技术之一，可用于访问芯片内的关键信息。可测试性和硬件安全性的要求是截然相反的。为了测试芯片，需要访问内部电路以将测试向量应用于所需的子电路并观察它们的响应。虽然这种完全访问被认为是制造测试的理想选择，但很明显，这种对设备内部电路的无限制访问可能会破坏其安全性。几十年来，硬件被认为是信任和安全的来源，但由于外包，这种假设不再成立。生产线的成本如此之高，以至于只有少数公司能够负担得起拥有内部生产线。将内部制造外包给海外代工厂为恶意活动提供了机会，并为被称为硬件木马的潜在安全威胁铺平了道路。当前的可测试性解决方案必须进行修改，以检测不需要的硬件修改并防止使用测试基础设施的安全漏洞。 这项工作的主要目标是推进新一代集成电路的可测试性设计和安全技术，以确保可测试性和硬件安全性，同时降低总体制造成本。本研究计划的具体目标是： (a) 使用基于 RFID 的身份验证开发 3D IC 的安全可测试性方法设计。 (b) 实施测试技术来检测硬件木马。 (c) 开发 3D 堆叠 IC 的预键合测试解决方案。 (d) 开发基于 FinFET 的电路的故障模型。