Advanced synthesiser techniques for mobile communications.

用于移动通信的先进合成器技术。

• 批准号: EP/D05012X/1
• 负责人: Paul Brennan
• 金额: $ 27.2万
• 依托单位: University College London
• 依托单位国家: 英国
• 项目类别: Research Grant
• 财政年份: 2006
• 资助国家: 英国
• 起止时间: 2006 至 无数据
• 项目状态: 已结题
• 来源: https://gtr.ukri.org/projects?ref=EP%2FD05012X%2F1
• 关键词: Advanced; synthesiser; techniques; mobile; communications.

Modern communications products, from TV sets to mobile phones, universally use a circuit known as a frequency synthesiser to generate a range of frequencies to allow the product to tune to different channels. In many applications, particularly mobile communications, these synthesisers need to produce very pure signals and simultaneously be able to change channels rapidly. These requirements are becoming increasingly demanding and often entail the use of multiple synthesiser loops in order to achieve the desired performance. More recently, a technique known as fractional-N synthesis has been developed to achieve this function using just a single synthesiser - a single-loop solution. This can tune very quickly, but tends to be noisy and, as a result, more advanced techniques have been applied, particularly sigma-delta modulation, to attempt to control this noise. However, there are still problems with this approach in terms of phase noise (a type of random noise) and discrete fractional spurs (individual tones).The proposed research involves investigation of three separate techniques, each originating from the applicants at UCL, to improve the performance of single-loop frequency synthesisers with the aim of rivalling or exceeding that of current multi-loop systems. The benefits of this would be a simplified, more compact and more economical implementation offering the same high performance. Since these circuits are very widely used, the commercial impact could be considerable. The first technique, known as stored-sequence synthesis, involves mimicking the behaviour of conventional sigma-delta fractional-N synthesisers by calculating the required bit sequences used to control the loop divider and storing them in memory. This is then read out at very high speed to produce the desired division ratio and hence channel frequency. The high speed and ability to generate and optimise the bit sequences off-line, offer major advantages in spectral purity and tuning speed and should provide an order of magnitude improvement over existing designs. The second part of the proposed project builds on our recent pioneering theoretical work on intermodulation effects in fractional-N synthesisers, in which we have discovered that a combination of natural phenomena (intermodulation and aliasing) are able to produce a family of discrete spurs at exactly the same frequencies as those due to a well known mechanism in a different part of the system, the modulator. This suggests that the phenomenon we have discovered may be an important and fundamental limitation on performance that has so far been completely overlooked; we would like to compare our theoretical work with experimental results from a carefully-designed test circuit to determine the true significance of this mechanism. This work may offer the opportunity to control the effects of such intermodulation and so improve performance. The final aim of the proposed research is to apply our experience in non-linear modelling of electronic systems, particularly sigma-delta ADCs (the subject of a previous EPSRC award) and chaos in PLLs, to develop a generic set of tools with which to obtain optimised fractional-N frequency synthesiser modulator designs and thus provide a scientific solution to what is currently something of a 'cut and try' design process.

从电视机到手机的现代通信产品，普遍使用称为频率合成器的电路来生成一系列频率，以允许产品调整到不同的频道。在许多应用程序（尤其是移动通信）中，这些合成器需要产生非常纯正的信号，并同时能够迅速更改通道。这些要求变得越来越苛刻，通常需要使用多个合成器循环，以实现所需的性能。最近，已经开发了一种称为分数-N合成的技术来仅使用单个合成器 - 单循环解决方案来实现此功能。这可以很快调整，但是趋于嘈杂，因此，已经应用了更先进的技术，尤其是Sigma-Delta调制，以尝试控制这种噪声。但是，这种方法在相位噪声（一种随机噪声）和离散的分数马刺方面仍然存在问题。拟议的研究涉及研究三种独立的技术，每种技术源自UCL的申请人，以提高单循环频率合成器的性能，以竞争或超过当前型型型环境的目的。这将是一种简化，更紧凑，更经济的实施，提供相同的高性能。由于这些电路非常广泛地使用，因此商业影响可能会很大。第一种技术称为存储序列合成，涉及模仿传统的Sigma-Delta分数-N合成器的行为，通过计算用于控制循环分隔器并将其存储在内存中的所需位序列。然后以非常高的速度读出，以产生所需的分裂比，从而产生通道频率。高速和生成和优化位序列离线，提供光谱纯度和调音速度的主要优势的能力，应比现有设计提供数量级的改进。拟议项目的第二部分建立在我们最近的开创性的理论工作上，该研究对分数-N合成器中的间隔效应的效果的理论工作为基础，在该研究中，我们发现自然现象的组合（交换和混叠）能够在系统中与模型不同的机构中的一个众所周知的机构产生与已知的频率相同的频率的家族。这表明我们发现的现象可能是对绩效的重要且基本的限制，到目前为止，这一局限性被完全忽略了。我们想将我们的理论工作与经过精心设计的测试电路的实验结果进行比较，以确定这种机制的真正意义。这项工作可能提供了控制这种交流的影响并提高性能的机会。 The final aim of the proposed research is to apply our experience in non-linear modelling of electronic systems, particularly sigma-delta ADCs (the subject of a previous EPSRC award) and chaos in PLLs, to develop a generic set of tools with which to obtain optimised fractional-N frequency synthesiser modulator designs and thus provide a scientific solution to what is currently something of a 'cut and try' design process.

项目成果

Memory-controlled frequency divider for fractional-N synthesisers

用于分数 N 合成器的内存控制分频器

• DOI: 10.1049/el:20062103
• 发表时间: 2006
• 期刊: Electronics Letters
• 影响因子: 1.1
• 作者: Brennan P

A New Mechanism Producing Discrete Spurious Components in Fractional-$N$ Frequency Synthesizers

在小数$N$频率合成器中产生离散杂散分量的新机制

• DOI: 10.1109/tcsi.2008.916694
• 发表时间: 2008
• 期刊: Regular Papers
• 作者: Brennan P

Minimax robust jamming techniques based on signal-to-interference-plus-noise ratio and mutual information criteria

基于信号干扰加噪声比和互信息准则的极小极大鲁棒干扰技术

• DOI: 10.1049/iet-com.2013.1054
• 发表时间: 2014-07-03
• 期刊: IET COMMUNICATIONS
• 影响因子: 1.6
• 作者: Wang, Lulu;Wang, Hongqiang;Brennan, Paul V.
• 通讯作者: Brennan, Paul V.