Communication Centric Microelectronic Design

以通信为中心的微电子设计

• 批准号: EP/D036895/1
• 负责人: Simon Moore
• 金额: $ 60.4万
• 依托单位: University of Cambridge
• 依托单位国家: 英国
• 项目类别: Research Grant
• 财政年份: 2006
• 资助国家: 英国
• 起止时间: 2006 至 无数据
• 项目状态: 已结题
• 来源: https://gtr.ukri.org/projects?ref=EP%2FD036895%2F1
• 关键词: Communication; Centric; Microelectronic; Design

We wish to undertake research into communication centricmicroelectronic design methods which are in contrast to today'scomputation centric (or gate-level) techniques. We believe thatthis research is timely since electronics is at the cusp of change.For the last 60 years, digital gates have been costly to produce andhave limited performance. We are now entering an era where the wires,which were once almost free, becoming the cost and performancelimiter. This trend is well documented in the InternationalTechnology Roadmap for Semiconductors (ITRS) roadmap which clearlyidentifies the step change needed in circuits and associated designtechniques. They also identify spiralling design complexity,escalating power densities and associated thermal problems.We believe that networks-on-chip resolve many of the design challengesfor future nano CMOS implementation technologies. Our backgroundresearch in this area has already resulted in a low latencynetwork-on-chip architecture which we have fabricated on 180nm CMOS.This initial work focused on interconnect between a tiled processorarchitecture which we have been developing with MIT. However, forthis project we wish to go much further, looking at communication atmany levels and for a range of technologies, from ASIC design on CMOSchips through to new field programmable gate array (FPGA)architectures. FPGA architecture is a departure from our usual lineof research, so we have been particularly grantified to receivea fully funded PhD studentship from Altera UK (one of the two biginternational FPGA companies) who will collaborate with us on thisproject.

我们希望对与当今的以计算为中心（或门级）技术形成鲜明对比的通信为中心的沟通研究方法进行研究。我们认为，由于电子产品处于变化的风口浪尖，因此这项研究是及时的。在过去的60年中，数字大门生产有限的性能成本很高。我们现在进入一个曾经是免费的电线的时代，成为成本和表演仪。这种趋势在国际技术路线图（ITRS）路线图中有充分的记录，该路线图清楚地识别了电路和相关设计技术所需的步骤变化。他们还确定了螺旋设计的复杂性，升级的功率密度和相关的热问题。我们相信，芯片上的网络解决了许多设计挑战，即未来的Nano CMOS实施技术。我们在该领域的背景研究已经导致了我们在180nm CMOS上制造的片段架构的低延迟网络架构。这本最初的工作着重于我们与MIT开发的瓷砖处理方法之间的互连。但是，我们希望进一步发展，从CMOSCHIPS上的ASIC设计到新的现场可编程Gate Array（FPGA）体系结构。 FPGA架构与我们通常的LineOf研究背道而驰，因此，我们将特别授予Altera UK（两家巨型FPGA公司之一）的应收取全额资助的博士生资金，他们将与我们合作。

项目成果

Implications of Rent's Rule for NoC Design and Its Fault-Tolerance

• DOI: 10.1109/nocs.2007.26
• 发表时间: 2007-05
• 期刊: First International Symposium on Networks-on-Chip (NOCS'07)
• 作者: Daniel Greenfield;A. Banerjee;Jeong-Gun Lee;S. Moore

A Communication Characterisation of Splash-2 and Parsec

• DOI: 10.1109/iiswc.2009.5306792
• 发表时间: 2009-01-01
• 期刊: PROCEEDINGS OF THE 2009 IEEE INTERNATIONAL SYMPOSIUM ON WORKLOAD CHARACTERIZATION
• 作者: Barrow-Williams, Nick;Fensch, Christian;Moore, Simon
• 通讯作者: Moore, Simon

Flow-aware allocation for on-chip networks

• DOI: 10.1109/nocs.2009.5071466
• 发表时间: 2009-05
• 期刊: 2009 3rd ACM/IEEE International Symposium on Networks-on-Chip
• 作者: A. Banerjee;S. Moore

Implications of Electronics Technology Trends to Algorithm Design

电子技术趋势对算法设计的影响

• 发表时间: 2009
• 期刊: The Computer Journal
• 作者: D Greenfield

RasP: An Area-efficient, On-chip Network

RasP：区域高效的片上网络

• DOI: 10.1109/iccd.2006.4380795
• 发表时间: 2006
• 作者: Hollis S