Communication Centric Microelectronic Design

以通信为中心的微电子设计

• 批准号: EP/D036895/1
• 负责人: Simon Moore
• 金额: $ 60.4万
• 依托单位: University of Cambridge
• 依托单位国家: 英国
• 项目类别: Research Grant
• 财政年份: 2006
• 资助国家: 英国
• 起止时间: 2006 至 无数据
• 项目状态: 已结题
• 来源: https://gtr.ukri.org/projects?ref=EP%2FD036895%2F1
• 关键词: Communication; Centric; Microelectronic; Design

We wish to undertake research into communication centricmicroelectronic design methods which are in contrast to today'scomputation centric (or gate-level) techniques. We believe thatthis research is timely since electronics is at the cusp of change.For the last 60 years, digital gates have been costly to produce andhave limited performance. We are now entering an era where the wires,which were once almost free, becoming the cost and performancelimiter. This trend is well documented in the InternationalTechnology Roadmap for Semiconductors (ITRS) roadmap which clearlyidentifies the step change needed in circuits and associated designtechniques. They also identify spiralling design complexity,escalating power densities and associated thermal problems.We believe that networks-on-chip resolve many of the design challengesfor future nano CMOS implementation technologies. Our backgroundresearch in this area has already resulted in a low latencynetwork-on-chip architecture which we have fabricated on 180nm CMOS.This initial work focused on interconnect between a tiled processorarchitecture which we have been developing with MIT. However, forthis project we wish to go much further, looking at communication atmany levels and for a range of technologies, from ASIC design on CMOSchips through to new field programmable gate array (FPGA)architectures. FPGA architecture is a departure from our usual lineof research, so we have been particularly grantified to receivea fully funded PhD studentship from Altera UK (one of the two biginternational FPGA companies) who will collaborate with us on thisproject.

我们希望研究以通信为中心的微电子设计方法，这与当今以计算为中心（或门级）技术形成鲜明对比。我们相信这项研究是及时的，因为电子学正处于变革的风口浪尖。过去 60 年来，数字门的生产成本高昂且性能有限。我们现在正在进入一个时代，曾经几乎免费的电线成为成本和性能的限制因素。这一趋势在国际半导体技术路线图 (ITRS) 中得到了详细记录，该路线图清楚地确定了电路和相关设计技术所需的阶跃变化。他们还确定了不断上升的设计复杂性、不断上升的功率密度以及相关的热问题。我们相信片上网络解决了未来纳米 CMOS 实现技术的许多设计挑战。我们在这一领域的背景研究已经产生了一种低延迟片上网络架构，该架构是在 180nm CMOS 上制造的。这项初步工作侧重于我们与 MIT 一起开发的平铺处理器架构之间的互连。然而，对于这个项目，我们希望走得更远，着眼于许多级别的通信和一系列技术，从 CMOS 芯片上的 ASIC 设计到新的现场可编程门阵列 (FPGA) 架构。 FPGA 架构与我们通常的研究方向不同，因此我们特别有幸获得英国 Altera（两大国际 FPGA 公司之一）提供的全额博士生奖学金，他们将与我们合作开展这个项目。

项目成果

Implications of Rent's Rule for NoC Design and Its Fault-Tolerance

• DOI: 10.1109/nocs.2007.26
• 发表时间: 2007-05
• 期刊: First International Symposium on Networks-on-Chip (NOCS'07)
• 作者: Daniel Greenfield;A. Banerjee;Jeong-Gun Lee;S. Moore

Flow-aware allocation for on-chip networks

• DOI: 10.1109/nocs.2009.5071466
• 发表时间: 2009-05
• 期刊: 2009 3rd ACM/IEEE International Symposium on Networks-on-Chip
• 作者: A. Banerjee;S. Moore

A Communication Characterisation of Splash-2 and Parsec

• DOI: 10.1109/iiswc.2009.5306792
• 发表时间: 2009-01-01
• 期刊: PROCEEDINGS OF THE 2009 IEEE INTERNATIONAL SYMPOSIUM ON WORKLOAD CHARACTERIZATION
• 作者: Barrow-Williams, Nick;Fensch, Christian;Moore, Simon
• 通讯作者: Moore, Simon

Implications of Electronics Technology Trends to Algorithm Design

电子技术趋势对算法设计的影响

• 发表时间: 2009
• 期刊: The Computer Journal
• 作者: D Greenfield

RasP: An Area-efficient, On-chip Network

RasP：区域高效的片上网络

• DOI: 10.1109/iccd.2006.4380795
• 发表时间: 2006
• 作者: Hollis S