Implementation of a High-Performance Multiple-Valued Current-Mode VLSI System with Low-Power and Highly Reliable Capabilities

具有低功耗和高可靠性功能的高性能多值电流模式 VLSI 系统的实现

基本信息

批准号：
12680324
负责人：
HANYU Takahiro
金额：
$ 2.37万
依托单位：
Tohoku University
依托单位国家：
日本
项目类别：
Grant-in-Aid for Scientific Research (C)
财政年份：
2000
资助国家：
日本
起止时间：
2000 至 2002
项目状态：
已结题

项目摘要

Low-power circuit design while maintaining a high-speed capability is needed not only for battery-powered portable applications but also to reduce the power dissipation of dedicated apecial-purpose VLSI processors, because the extra current density in interconnections causes temporal or permanent malfunction due to voltage drops or electromigrations. Multiple-valued current-mode (MVCM) integrated circuits have a potential advantage to reduce the wiring complexity and the nurnber of active devices in arithmetic large-scale-integration chips because the frequently used linear sum operation can be performed simply by wiring with no active devices. However, the switching speed in the MVCM circuit is relatively slow, and its power dissipation due to the steady current becomes high because current-sources in differential-pair circuits always flow a constant current in the active mode. In this project, a new MVCM circuit based on dual-rail differential logic has been proposed for high-speed, … More low-power, highly reliable arithmetic-oriented VLSI. A differential logic-style circuit has an attractive feature that its input voltage swing is small enough while maintaining a high currentdriving capability. The combination of the differential logic style and MVCM circuitry in arithmetic VLSI makes it possible to improve the switching speed compared with that of a corresponding binary CMOS implementation. Moreover, the use of a precharge-evaluate logic style abo makes the steady current flow cut off, which results in great reduction of dynamic power dissipation. A judicious combination of differential logic, MVCM logic and dynamic logic in the proposed circuit makes it possible to reduce the power dissipation together with device and interconnection counts while maintaining a high-speed switching capability. The use of dual-rail coding, which is used in differential logic-style circuit, is a widely used encoding style of asynchronous and self-checking circuit implementation. From this point of view, we have also proposed high-performance asynchronous and self-checking circuit using multiple-valued dual-rail complementary signals. Less

低功耗电路设计同时保持高速能力不仅对于电池供电的便携式应用来说是必需的，而且对于减少专用的VLSI处理器的功耗来说也是如此，因为互连中的额外电流密度会导致暂时或永久故障。多值电流模式（MVCM）集成电路具有潜在的优势，可以减少算术大规模集成芯片中的布线复杂性和有源器件数量。所使用的线性求和运算只需通过布线即可完成，无需有源器件。然而，MVCM电路中的开关速度相对较慢，并且由于差分对电路中的电流源总是流动，因此其稳定电流导致的功耗变高。在该项目中，提出了一种基于双轨差分逻辑的新型 MVCM 电路，用于高速、低功耗、高可靠性的面向算术的 VLSI 差分逻辑型电路。有一个有吸引力的其特点是输入电压摆幅足够小，同时保持高电流驱动能力。与相应的二进制 CMOS 实现相比，算术 VLSI 中差分逻辑类型和 MVCM 电路的结合使得可以提高开关速度。使用预充电评估逻辑类型 abo 可以切断稳定电流，从而大大降低动态功耗。在所提出的电路中，微分逻辑、MVCM 逻辑和动态逻辑的明智组合使其成为可能。减少功耗以及器件和互连数量，同时保持高速开关能力。双轨编码用于差分逻辑式电路，是一种广泛使用的异步自检编码方式。从这个角度出发，我们还提出了采用多值双轨互补信号的高性能异步自检电路。