MULTIPLE-VALUED PROCESSOR FOR INTELLIGENT INTEGRATED SYSTEM

智能集成系统多值处理器

基本信息

批准号：
09044125
负责人：
HANYU Takahiro
金额：
$ 1.98万
依托单位：
TOHOKU UNIVERSITY
依托单位国家：
日本
项目类别：
Grant-in-Aid for international Scientific Research
财政年份：
1997
资助国家：
日本
起止时间：
1997 至 1998
项目状态：
已结题

项目摘要

Real-world applications need to achieve very quick response for dynamically changing real-world environment. Therefore, it is very important to develop a "Super Chip for Intelligent Integrated Systems." The emerging technologies of intelligent integrated systems for real-world applications rely increasingly on VLSI processors high degree of parallelism in various levels such as architectural, logic design, and circuit/device level. The following items are the themes discussed in this project : (1)Discussion about algorithm/system/architecture-level innovation : We have discussed about the efficiency of multiple-valued logic-in-memory VLSI as the development of fully parallel image processor for intelligent integrated systems. The basic idea of the multiple-valued logic-in-memory VLSI architecture is that the data which are frequently used in the communication between the processing element (PE) and the memory are stored into the local memory tightly connected to the PE.We also discussed about the efficiency of some concrete examples using such concept.(2)Discussion about logic-design/circuit-design-level innovation : We have presented a floating-gate-MOS pass-transistor network as a circuit-level logic-in-memory VLSI architecture. We have discussed about the usefulness of such a new pass-transistor network and about its application areas. While a floating-gate MOS transistor is used as a multiple-valued storage element in the present VLSI system, some logical functions such as a threshold function and a pass-switch function are merged into the multiple-valued memory plane.(3)Discussion about device/process-technology-level innovation : We have also discussed about the device technologies to realize the floating-gate-MOS pass-transistor network.

现实世界的应用程序需要对动态变化的现实环境实现非常快速的响应。因此，开发“智能集成系统超级芯片”非常重要。用于实际应用的智能集成系统的新兴技术越来越依赖于架构、逻辑设计和电路/设备级别等各个级别的VLSI处理器的高度并行性。本项目讨论的主题如下： (1)关于算法/系统/架构级创新的讨论：我们讨论了多值逻辑内存VLSI作为全并行图像处理器的开发的效率。智能集成系统。多值内存逻辑VLSI架构的基本思想是将处理元件（PE）和存储器之间通信中频繁使用的数据存储到与PE紧密连接的本地存储器中。讨论了使用这种概念的一些具体示例的效率。（2）关于逻辑设计/电路设计级创新的讨论：我们提出了一种浮栅MOS传输晶体管网络作为电路级逻辑输入存储器VLSI架构。我们已经讨论了这种新型传输晶体管网络的实用性及其应用领域。在当前的VLSI系统中，浮栅MOS晶体管被用作多值存储元件，一些逻辑功能，例如阈值功能和传输开关功能被合并到多值存储平面中。 (3)讨论关于器件/工艺技术层面的创新：我们还讨论了实现浮栅MOS传输晶体管网络的器件技术。