Set-Valued-Logic VLSI Architecture for Highly Parallel Computation

用于高度并行计算的集值逻辑 VLSI 架构

基本信息

批准号：
10680329
负责人：
AOKI Takafumi
金额：
$ 2.3万
依托单位：
Tohoku University
依托单位国家：
日本
项目类别：
Grant-in-Aid for Scientific Research (C)
财政年份：
1998
资助国家：
日本
起止时间：
1998 至 2000
项目状态：
已结题

来源：
https://kaken.nii.ac.jp/grant/KAKENHI-PROJECT-10680329/
关键词：
Hardware Algorithms Integrated Circuits VLSI Multiple-Valued Logic Set-Valued Logic CDMA Code-Division Multiple Access Neural Networks 理論回路並列処理

项目摘要

Interconnection problems have been recognized as basic limitations in present-day VLSI systems. This research project is to investigate a possibility of solving the interconnection problems by employing new VLSI architectures based on multiple-valued logic (MVL) and set-valued logic (SVL). Listed below are major results of this project :1. The basic SVL gates employing binary m-sequences as information carriers were proposed.A systematic technique for synthesizing S VL circuits with the basic logic gates was investigated.2. A highly reliable SVL system employing distributed signal representation with binary m-sequences was proposed.3. A method of implementing SVL circuits using bi-directional current-mode CMOS technology was proposed. A 9x9-pixel template matching circuit for image processing was fabricated with 0.6um CMOS technology. It was shown that 30% reduction in chip area and 78% reduction in wire area could be achieved by SVL technology for 40x40-pixel template matching.4. A new type of highly parallel neural network architecture employing m-sequences as signal carriers was proposed.5. The concept of SVL was extended into a general framework of intra/inter-chip CDMA communication using orthogonal information carriers. A phase-offset-error-free CDMA technique based on multiple-valued m-sequences was investigated for efficient data transmission in VLSI systems.6. Various hardware algorithms and VLSI architectures based on MVL were also investigated to compare fundamental properties of MVL and SVL.Our initial observation shows that SVL (or CDMA) is suitable for analog signal transmission/processing as well as large-scale inter-chip communication, while MVL is suitable for digital arithmetic computation with lower processing granularity.Further investigations on MVL/SVL-based VLSI architectures for large-scale applications are being left as future research subjects.

互连问题已被认为是当今 VLSI 系统的基本限制。该研究项目旨在研究通过采用基于多值逻辑（MVL）和集值逻辑（SVL）的新型VLSI架构来解决互连问题的可能性。本项目的主要成果如下： 1．提出了以二进制m序列作为信息载体的基本SVL门。研究了用基本逻辑门合成SVL电路的系统技术。 2．提出了一种采用二进制m序列分布式信号表示的高可靠SVL系统。 3．提出了一种利用双向电流模式CMOS技术实现SVL电路的方法。采用0.6um CMOS技术制作了用于图像处理的9x9像素模板匹配电路。结果表明，采用SVL技术进行40x40像素模板匹配，芯片面积可减少30%，布线面积可减少78%。 4．提出了一种采用m序列作为信号载体的新型高度并行神经网络结构。 5． SVL的概念被扩展到使用正交信息载体的芯片内/芯片间CDMA通信的通用框架。研究了一种基于多值m序列的无相位偏移误差CDMA技术，以实现VLSI系统中的高效数据传输。 6．还研究了基于 MVL 的各种硬件算法和 VLSI 架构，以比较 MVL 和 SVL 的基本特性。我们的初步观察表明，SVL（或 CDMA）适用于模拟信号传输/处理以及大规模芯片间通信，而MVL适合处理粒度较低的数字算术计算。针对大规模应用的基于MVL/SVL的VLSI架构的进一步研究将作为未来的研究课题。