Research on Code Generation Algorithms for Retargetable Compilers for DSPs

DSP可重定向编译器代码生成算法研究

• 批准号: 11680355
• 负责人: ISHIURA Nagisa
• 金额: $ 2.24万
• 依托单位: Osaka University
• 依托单位国家: 日本
• 项目类别: Grant-in-Aid for Scientific Research (C)
• 财政年份: 1999
• 资助国家: 日本
• 起止时间: 1999 至 2000
• 项目状态: 已结题
• 来源: https://kaken.nii.ac.jp/grant/KAKENHI-PROJECT-11680355/
• 关键词: retargetable compiler; DSP; digital signal processing; embedded processor; codesign

In this project, we conducted a research on code generation problem for retargetable compilers for DSPs (digital signal processors). We formalized a code generation problem, developed algorithms to solve this problem, and developed a prototype compiler based on the algorithms.The task of code generation consists of three phases : 1) instruction selection, 2) binding, and 3) scheduling. As for 1), we developed a rule based method of rewriting dataflow graphs. As for 2) we developed a heuristic algorithm to minimize the number of the additional data transfer operations and yet to maximize the parallelism among operations. As for 3), we solved the difficulty with respect to the register capacity constraints by introducing a register constraints analysis phase before list-based scheduling. We also proposed an analysis method of minimizing spill codes.We implemented a prototype compiler by which we compiled a G.723.1 speech codec program written in C language, targeting various datapath configuration with differenet numbers of MAC units or different bus configurations. It was found that we can observe the trade-off between the hardware costs and the number of execution cycles.

在这个项目中，我们针对DSP（数字信号处理器）的可重复编译器的代码生成问题进行了研究。我们对代码生成问题进行了形式化，开发了解决此问题的算法，并根据算法开发了原型编译器。代码生成的任务包括三个阶段：1）指令选择，2）绑定和3）调度。至于1），我们开发了一种基于规则的重写数据流图的方法。至于2）我们开发了一种启发式算法，以最大程度地减少附加数据传输操作的数量，并尚未最大程度地提高操作之间的并行性。至于3），我们通过在基于列表的调度之前引入寄存器约束分析阶段来解决对寄存器容量约束的难度。我们还提出了一种最小化溢出代码的分析方法。我们实施了一个原型编译器，通过该编译器，我们编制了用C语言编写的G.723.1语音编解码器程序，针对具有不同的MAC单位数量或不同总线配置的各种数据配置。发现我们可以观察硬件成本与执行周期数量之间的权衡。

项目成果

Mizuki Takahashi, Nagisa Ishiura Akihisa Yamada, and Takashi Kambe: "Thread Composition Method for Hardware Compiler Bach Maximizing Resource Sharing among Processes"IEICE Trans.Fundamentals. vol.E83-A, no.12. 2456-2463 (2000)

Mizuki Takahashi、Nagisa Ishiura Akihisa Yamada 和 Takashi Kambe：“硬件编译器 Bach 最大化进程间资源共享的线程组合方法”IEICE Trans.Fundamentals。

Nagisa Ishiura, Tatsuo Watanabe, and Masayuki Yamaguchi: "A Code Generation Method for Datapath Oriented Application Specific Professor Design"in Proc.Workshop on Synthesis and System Integration of Mixed Technologies (SASIMI 2000), Kyoto, Japan. 71-78 (2

Nagisa Ishiura、Tatsuo Watanabe 和 Masayuki Yamaguchi：“A Code Generation Method for Datapath Oriented Application Specific Professor Design”，Proc.Workshop on Synthesis and System Integration of Mixed Technologies (SASIMI 2000)，日本京都。