Hardware Description Language-Oriented Analog/Digilal Mixed-Signal Multilevel Circuit Simulator

硬件描述面向语言的模拟/数字混合信号多级电路模拟器

• 批准号: 11650409
• 负责人: ASAI Hideki
• 金额: $ 2.37万
• 依托单位: Shizuoka University
• 依托单位国家: 日本
• 项目类别: Grant-in-Aid for Scientific Research (C)
• 财政年份: 1999
• 资助国家: 日本
• 起止时间: 1999 至 2001
• 项目状态: 已结题
• 来源: https://kaken.nii.ac.jp/grant/KAKENHI-PROJECT-11650409/
• 关键词: hardware description language; analog; digital mixed-signal; multilevel simulator; behavioral model; 3-dimensional interconnect model; macromodel; electromagnetic field simulation; signal; power integrity; FDTD法; 伝送線路シミュレータ; 時間領域マクロモデル; モデル・リ

Progress of integration and high-frequency techniques demands that circuit simulator has toI) deal with analog/digital mixed signals for analog/digital mixed LSLs,II) deal with the electromagnetic field effects for the verification of signal/power integrity,III) use the behavioral models for the verification of large-scale system.Therefore, we need the analog/digital mixed-mode multilevel circuit simulator, which can deal with behavioral model of the functional block From 1999 to 2000, in this research project, we have developed the multilevel simulator, which1) can use hardware description language ASSIST-alpha, which has been written in C/C++ language,2) includes the FDTD-based electromagnetic field solver,3) includes the synthesizer for macromodeling of 3-dimensional interconnectFurthermore, from 2000 to 2001, we have improved the above simulator by addition of4) acceleration techniques of 3-dimensional electromagnetic field solver based on FDTD method,5) macromodeling method from data obtained by 3-dimensional simulation,6) modeling and simulation techniques based on analog hardware description language, and developed the prototype of mixed-mode multilevel simulator which is applicable to verification of signal integrity.

整合和高频技术的进展要求电路模拟器对模拟/数字混合LSL进行类似/数字混合信号处理，ii）处理信号/功率完整性的电磁场效应，iii iii，iii）使用行为模型，以便对大型模型进行验证，然后进行数字模型，然后进行类似模型，默认模型，默认模型，默认模型。从1999年到2000年，在该研究项目中，我们开发了多层次模拟器，其中1）可以使用硬件说明语言辅助-Alpha（用C/C ++语言编写），2）包括基于FDTD的电气磁性求解器，3）包括在2001年间隔的三个级别的互联剂，包括2000年度的合成器，从通过添加4）基于FDTD方法的3维电磁现场求解器的加速技术，5）通过3维模拟获得的数据，基于模拟和模拟技术，基于模拟硬件说明语言，并开发了混合模层模拟器的原型，从而适用于信号的Verifection verized verized verized verigation verefections compections verigation verized verized verigation versemptions compections compection versige。

项目成果

浅井秀樹: "SoC/SiP設計に向けたEDAシステムの将来像"電気学会電子回路研究会資料. ECT-02-46. 29-34 (2002)

Hideki Asai：“SoC/SiP 设计的 EDA 系统的未来形象”IEEJ 电子电路研究组材料。 ​​ECT-02-46 (2002)。

Hidemasa Kubota: "Noise Analysis of Power/Ground Planes on PCB by SPICE-Like Simulator with Model Order Reduction Technique"Proc. IEEE 2002 Int. Symp. on Circuits and Syst.. (to appear). (2002)

Hidemasa Kubota：“采用模型降阶技术的类 SPICE 模拟器对 PCB 上的电源/接地层进行噪声分析”Proc。

Pornanong Pongpaibool: "An Alternating Implicit Block Overlapped FDTD (AIBO-FDTD) Method and Its Estimation with Parallel Computation"Proc. IEEE 10^<th> Topical Meeting on Electrical Performance of Electronic Packaging. 185-188 (2001)

Pornanong Pongpaibool：“一种交替隐式块重叠 FDTD (AIBO-FDTD) 方法及其并行计算估计”Proc。

M. Suzuki: "A Synthesis Technique of Time-Domain Interconnect Models by MIMO Type of Selective Orthogonal Least Square Method"IEEE Trans. on Microwave Theory & Techniques. Vol.49, No.10. 1708-1714 (2001)

M. Suzuki：“基于MIMO型选择性正交最小二乘法的时域互连模型综合技术”IEEE Trans。

H. Kubota: "Analysis of power/ground planes by PCB simulator with model order reduction technique"Proc. IEEE10th Topical Meeting on Electrical Performance of Electronic Packaging. 77-80 (2001)

H. Kubota：“采用模型降阶技术的 PCB 模拟器对电源/接地层进行分析”Proc。