Research on Digitalized Spread Spectrum Communication System Using Real-Valued Sequences

利用实值序列的数字化扩频通信系统研究

基本信息

批准号：
10650365
负责人：
TADANO Yoshihiro
金额：
$ 1.6万
依托单位：
Yamaguchi University
依托单位国家：
日本
项目类别：
Grant-in-Aid for Scientific Research (C)
财政年份：
1998
资助国家：
日本
起止时间：
1998 至 1999
项目状态：
已结题

来源：
https://kaken.nii.ac.jp/grant/KAKENHI-PROJECT-10650365/
关键词：
Spread spectrum communication CDMA Orthogonal finite-length sequence Interchannel interference Intersymbol interference Fast correlation Digital signal processing FPGA 高速相閲

项目摘要

This project has been performed from 1998 to 1999, for the purpose of developing real-valued sequences for a quasi-synchronous CDMA system with no interchannel interference and with little intersymbol interference and implementing trial degitalized modems for this CDMA system, to bring a novel technique to the current CDMA systems. The aim of this research is nearly attained. Digital fast processors of code generation and correlation are implemented on FPGA, because of construction of the real-valued sequences applicable to fast signal processing algorithm. Performances of correlation processing in the multiple access experiment almost follow those of designed values. The real-valued finite-length sequences developed in this research are effective to design the codes of high efficiency data transmission free from the guard interval to avoid interferences, and so expected to be developed to the future concrete application system.The achievements of this project are the followings.(1) Developments of the sequences for CDMA and the algorithm of fast correlationOrthogonal sets of real-valued finite-length sequences with sharp autocorrelation function are derived from the convolution of element sequences that leads to fast correlation algorithm.(2) Trial production of code generator and correlatorThe code generator using ROM and correlator using FPGA corresponding to 10,000 logic gates are implemented for the aproximated integer sequence from the real-valued shift-orthogonal finite-length sequence of length 33.The combining operation of 8-bit generator output and 8-bit correlator input presents 16Mchips/s rate and correlation pulse of 1% error.(3) Experiment of CDMA transmissionThe experiment of optical and spatial multiplexing transmission based on two real-valued finite-length sequences shows that 0dB D/U ratio at the correlator input is improved to 40dB D/U ratio at its output, satisfying the orthogonality within allowable error.

该项目于1998年至1999年进行，目的是为无通道间干扰和符号间干扰的准同步CDMA系统开发实值序列，并为该CDMA系统实现试用去数字化调制解调器，从而带来一种新技术到目前的CDMA系统。本次研究的目的已经基本达到了。由于构建了适用于快速信号处理算法的实值序列，因此在FPGA上实现了代码生成和相关的数字快速处理器。多址实验中相关处理的性能基本符合设计值。本研究开发的实值有限长序列可有效设计不受保护间隔避免干扰的高效数据传输编码，有望发展到未来的具体应用系统中。本课题的成果(1) CDMA序列和快速相关算法的发展从元素序列的卷积中导出具有尖锐自相关函数的实值有限长度序列的正交集，从而产生快速相关算法。(2)试生产代码生成器和相关器的使用ROM的代码生成器和使用FPGA的相关器实现了对应于10,000个逻辑门的从长度为33的实值移位正交有限长度序列的近似整数序列。8位生成器输出的组合操作8位相关器输入呈现16Mchips/s的速率和1%误差的相关脉冲。 (3)CDMA传输实验光和空间实验基于两个实值有限长度序列的复用传输表明，相关器输入端的0dB D/U比提高到输出端的40dB D/U比，在允许误差范围内满足正交性。