HIGH SPEED PARALLEL COMPUTER SYSTEM USING 3-DIMENTIONAL INTEGLATED SHARED MEMORY

使用3维集成共享存储器的高速并行计算机系统

• 批准号: 08505003
• 负责人: KOYANAGI Mitsumasa
• 金额: $ 24.06万
• 依托单位: TOHOKU UNIVERSITY
• 依托单位国家: 日本
• 项目类别: Grant-in-Aid for Scientific Research (A)
• 财政年份: 1996
• 资助国家: 日本
• 起止时间: 1996 至 1998
• 项目状态: 已结题
• 来源: https://kaken.nii.ac.jp/grant/KAKENHI-PROJECT-08505003/
• 关键词: Three Dimensional Integration Technology; Three Dimensional Integrated Shard Memory; High Speed parallel Computing System; Bus Bottle Neck; Parallel Monte Carlo Analysis; Device Simulation; Deca-nano device; ULSI

This project aimed to develop a compact parallel computer system specific for the Monte-Carlo simulation. The results are summarized as follows :1. Parallel computer system specific for the Monte-Carlo simulation. System ana1ysis of the first version parallel computer was completed on 1997. The second version has been designed since 1997. In second version, the communication bus and protocol are dramatically improved for speeding up the inter-processor communication. A new ring bus pipe line architecture is proposed and is introduced into the second version design. The data coming through the ring bus are processed at each processing unit in parallel and sent to next processing unit. Therefore, a combined system of ring bus and processing units act as a huge pipe line. The architecture level design has been completed.2. Three dimensional integration technologyThe following three key technologies have been developed for three-dimensional integrated circuit.(a) Micro-bump formationA new … More lift-off technology has been developed for the micro-bump formation. Indium(In)-gold(Au) micro-bumps as small as 5 mu m can be easily formed by using this technology. It was found that thin tungsten film inserted between In-Au micro-bump and aluminum electrode is very effective to reduce the contact resistance. A very low contact resistance of 0.05 OMEGA per micro-bump was obtained.(b) Wafer alignment and bondingSeveral wafers are stacked and bonded for three -dimensional integration after careful wafer alignment. A new vacuum adhesive injection method was developed for gluing the wafers. Liquid adhesive was injected into the small gap between two stacked wafers in vacuum ambient applying a mechanical pressure from both sides of wafers. Injected liquid adhesive was cured at 180ﾟC.This procesure improved the bondability of wafers and the electrical characteristics of micro-bumps.(c) Vertical interconnection and wafer thinningThe deep trench with the diameter of 3 mu m and the depth of 60 mum has been formed on a silicon substrate after optimizing the ICP(Inductively Coupled Plasma) etching condition. After the trench etching, oxidation, poly-silicon deposition, impurity diffusion and etching back of poly-silicon by CMP were performed. Thus, a low resistive vertical interconnection for three-dimensional integrated circuit has been successfully formed. Less

该项目旨在开发针对蒙特卡洛模拟的紧凑平行计算机系统。结果总结如下：1。平行计算机系统针对蒙特 - 卡洛模拟。第一个版本并行计算机的系统ana1sys于1997年完成。第二版是自1997年以来设计的。在第二版中，通信总线和协议得到了显着改进，以加快处理程序间的通信。提出了新的环形总线管线架构，并引入第二版设计。通过环总线的数据并行处理每个处理单元，并发送到下一个处理单元。因此，环形总线和处理单元的组合系统充当巨大的管道线。建筑级设计已完成2。三维集成技术已经为三维集成电路开发了以下三个关键技术。（a）微型造型组合新的……已经为微型倒数形成而开发了更多的升降技术。使用该技术很容易形成indium（in）-gold（au）微型降低至5 mu m。已经发现，在AU微型凹凸和铝电极之间插入的细钨膜对于降低接触电阻非常有效。获得非常低的接触电阻为每微凸ump的0.05欧米茄。（b）晶状比对和粘结性波被堆叠并粘合，以在仔细摇动对准后进行三维整合。开发了一种新的真空粘合剂注入方法，用于粘合波。在真空环境中，将液体粘合剂注入了两个堆叠波之间的小间隙，并从摇动的两侧施加机械压力。 Injected liquid adhesive was cured at 180ﾟC.This procedure improved the bondability of waves and the electric Characteristics of micro-bumps.(c) Vertical interconnection and wafer thinningThe deep trench with the diameter of 3 mu m and the depth of 60 mu m has been formed on a silicon substrate after optimizing the ICP (Inductively Coupled Plasma) etching condition.沟槽蚀刻后，进行了氧化，氧化，多丝硅沉积，杂质扩散和通过CMP对聚硅的蚀刻。这是成功形成的三维集成电路的低抗性垂直互连。较少的

项目成果

K.Sakuma,M.Koyanagi,et.al: "A New Wafer-Scale Chip-on-Chip(W-COC)Packaging Technology Using Adhesive Injection Method" Extended Abstracts of the 1998 Conference on Solid State Devices and Materials. 286-287 (1998)

K.Sakuma、M.Koyanagi 等人：“采用粘合剂注入方法的新型晶圆级片上芯片 (W-COC) 封装技术”1998 年固态器件和材料会议的扩展摘要。

D.Kawae H.Kurino M.Koyanagi: "Design of Real Time Micro-Vision System LSI with Three-Dimensional Structure" Proceedings.of the Workshop on Synthesis And System Integration of Mixed Technologies. 229-234 (1998)

D.Kawae H.Kurino M.Koyanagi：“具有三维结构的实时微视觉系统LSI的设计”混合技术综合与系统集成研讨会论文集。

T.Matsumoto Y.Noguchi Y.Kudoh M.Koyanagi: "Polyimide Optical Waveguide with Multi-Fan-Out for Multi-Chip Module Application" Jpn.J.Appl.Phys.Vol.36 Part 1, No.3B. 1903-1906 (1997)

T.Matsumoto Y.Noguchi Y.Kudoh M.Koyanagi：“用于多芯片模块应用的具有多扇出的聚酰亚胺光波导”Jpn.J.Appl.Phys.Vol.36 第 1 部分，No.3B。

M.Koyanagi H.Kurino T.Matsumoto K.Sakuma K.W.Lee N.Miyakawa H.Itani H.Tsukamoto: "New Three Dimensional Integration Technology for Future System-on-Silicon LSIs" IEEE International Workshop on Chip-Package Codesign CPD 1998. 96-103 (1998)

M.Koyanagi H.Kurino T.Matsumoto K.Sakuma K.W.Lee N.Miyakawa H.Itani H.Tsukamoto：“未来硅基 LSI 系统的新型三维集成技术”IEEE 国际芯片封装协同设计研讨会 CPD 1998。

H.Kurino T.Matsumoto M.Koyanagi 他4人: "Three-Dimensional Integration Technology for Real Time Micro-Vision System" Proc.of the Intern. Conf.on Innovative Systems in Silicon. 203-212 (1997)

H.Kurino T.Matsumoto M.Koyanagi 等 4 人：“实时微视觉系统的三维集成技术”Proc.of the Intern. on Innovative Systems in Silicon（硅创新系统）。