Implementation of a One-Transistor Multiple-Valued Content-Addressalbe Memory and Its Application

一种单晶体管多值内容寻址存储器的实现及其应用

• 批准号: 09558027
• 负责人: HANYU Takahiro
• 金额: $ 7.49万
• 依托单位: Tohoku Univesity
• 依托单位国家: 日本
• 项目类别: Grant-in-Aid for Scientific Research (B).
• 财政年份: 1997
• 资助国家: 日本
• 起止时间: 1997 至 2000
• 项目状态: 已结题
• 来源: https://kaken.nii.ac.jp/en/grant/KAKENHI-PROJECT-09558027/
• 关键词: Multiple-Valued CAM; Floating-Gate MOS Transistor; Threshold Operation; Logic-in-Memory Architecture; Non-numeric Data Processing; Highly-Parallel Operation; Magnitude Comparison; Intelligent Information Processing; フローティングゲートMOSトランジスタ; Multiple-Valued CAM; Floating-Gate MOS Transistor; Threshold Operation; Logic-in-Memory Architecture; Non-numeric Data Processing; Highly-Parallel Operation; Magnitude Comparison; Intelligent Information Processing; フローティングゲートMOSトランジスタ

Communication bottleneck between memory and logic modules is one of the most serious problems in the multimedia VLSI systems on a chip. A logic-in-memory structure, in which logic-circuit elements are distributed over a memory-cell array, is a key technology to solve the above problem. A content-addressable memory (CAM) is one of the typical logic-in-memory VLSIs. However, CAMs have been more complex to build and had lower storage density than a normal memory such as RAMs because of the overhead involved in the storage and logic elements.In this project, a high-performance multiple-valued CAM based on floating-gate-MOS pass-transistor logic is proposed to perform highly parallel magnitude comparisons in a limited chip area. Multiple-valued stored data in the proposed CAM correspond to the threshold voltage of a floating-gate MOS transistor, so that the CAM cell circuit can be designed by using only a single MOS transistor. Moreover, a logic-in-memory VLSI architecture based on such a multiple-valued floating-gate-MOS pass-transistor network is also proposed to realize parallel arithmetic and logic circuits with multiple-valued inputs and binary outputs. The main results of this project are listed below :(1) Highly Parallel Magnitude-Comparison Hardware Algorithm for CAMs,(2) Logic-in-Memory VLSI Architecture Using Floating-Gate MOS-Based Multiple-Valued Pass-Transistor Network,(3) Functional Pass Gate Based on Ferroelectric Devices and Their Application,(4) Current/Voltage-Hybrid-Mode Multiple-Valued Integrated Circuits.

内存和逻辑模块之间的通信瓶颈是芯片上多媒体VLSI系统中最严重的问题之一。逻辑中的逻辑结构，其中逻辑电流元素分布在内存细胞阵列上，是解决上述问题的关键技术。内容 - 可视内存（CAM）是典型的内存逻辑VLSIS之一。但是，凸轮的构建更为复杂，并且比正常内存（例如RAM）的存储密度较低，因为其间接费用涉及存储和逻辑元素。在该项目中，一个基于浮动式通行器传播器逻辑的高性能多价值凸轮可在有限的芯片筹码区域中执行高度平行的幅度。所提出的凸轮中的多价值存储的数据对应于浮顶MOS晶体管的阈值电压，因此CAM细胞电路只能通过仅使用单个MOS晶体管设计。此外，还提出了基于此类多价值的浮动门传递传播网络的逻辑VLSI体系结构，以实现具有多价值输入和二进制输出的并行算术和逻辑电路。该项目的主要结果如下列出：（1）使用基于浮动的MOS MOS基于MOS的多值密码传输网络，（3）基于铁电器设备及其应用程序的功能性通行门，（3）使用浮动通行门，（4）当前/VORTAGE-yytriD-hyybrid-hyybrid hyybrid hyybrid hyybrid hyybrid hyybrid hyybrid hyybrid hyybrid hyybrid hyybrid，（1）使用基于浮动的MOS的逻辑中的VLSI体系结构（2）cAM的高度平行幅度比较硬件算法，（3）功能通行门。