Implementation of a High-Speed Asynchronous Data Transfer VLSI Based on Bidirectional Current-Mode Multiple-Valued Circuit Techniques

基于双向电流模式多值电路技术的高速异步数据传输VLSI的实现

基本信息

批准号：
15500029
负责人：
HANYU Takahiro
金额：
$ 2.43万
依托单位：
Tohoku University
依托单位国家：
日本
项目类别：
Grant-in-Aid for Scientific Research (C)
财政年份：
2003
资助国家：
日本
起止时间：
2003 至 2005
项目状态：
已结题

项目摘要

The trend in global interconnection delay such as clock distribution is becoming a significant problem in recent deep submicron VLSI. As CMOS technology scales from one generation to the next, the product of the interconnect resistance and load capacitance is not scaling with technology. One of the possible methods to solve the above interconnection problems is to use asynchronous circuit implementation. Dual-rail encoding is widely used as an encoding style of asynchronous data transfer, where every logical variable is encoded using two wires and timing information is also implicit in the code. Every asynchronous data transfer protocol is based on request-acknowledge handshaking : every transfer features a request action where the initiator starts a transfer, and an acknowledge action allowing the target to respond. In this way, the signals propagate round trip between the transmitter and the receiver, thus the cycle time of data transfer becomes large, which is the problem accompanyi … More ng asynchronous data transfer essentially. If the above procedures are executed simultaneously, the cycle time of the asynchronous data transfer with dual-rail encoding becomes much faster than that of the conventional methods. In this research, a new asynchronous data-transfer protocol, called 2-color "1-pbase" dual-rail encoding, is proposed for high-speed asynchronous data transfer. The 2-color 1-phase encoding has two colors which mean two kinds of data definition "ODD" and "EVEN", and different valid data is detected by transferring codewords which have different color alternately. In this protocol, the receiver as well as the transmitter sends the color information as the request signal, then the data transfer is performed by detecting whether the mutual color information is same or not. Because the both request signals can be sent simultaneously, overlap communication can be done. Since data and color information must be bundled on the same wires in the asynchronous data transfer, it is important to detect valid data from the mixed dual-rail code of data and color information. The use of the proposed encoding makes it easy to merge and detect data and color information by calculating the sum of the codewords. In multiple-valued bidirectional current-mode circuits, since current-mode linear summation can be implemented by wiring without any active devices, the proposed asynchronous circuit becomes simple. Moreover, current signals from both sides can be superposed on the same wires, which is an important characteristic of multiple-valued current-mode logic to realize a control signal multiplexing scheme. The use of comparators with sense amplifier makes it easy to detect the sum of components of the codewords quickly. In fact, it is evaluated in a 0.18um CMOS technology that the data transfer cycle of the proposed asynchronous data-transfer scheme using the multiple-valued current-mode logic circuit is about 1.5-times faster than that of the corresponding binary CMOS implementation under the normalized power dissipation. Less

随着CMOS技术从一代扩展到下一代，诸如时钟分配之类的全局互连延迟的趋势正在成为重要问题之一。解决上述互连问题的可能方法是使用异步电路实现双轨编码作为异步数据传输的编码方式被广泛使用，其中每个逻辑变量都使用两条线进行编码，并且时序信息也隐含在代码中。每一个异步数据传输协议基于请求-确认握手：每次传输都具有发起者开始传输的请求操作和允许目标响应的确认操作，通过这种方式，信号在发送器和接收器之间传播。，因此数据传输的周期时间变长，这本质上是异步数据传输的问题，如果同时执行上述过程，则双轨编码的异步数据传输的周期时间会变得更快。的传统方法。在本研究中，提出了一种新的异步数据传输协议，称为2色“1-pbase”双轨编码，用于高速异步数据传输。2色1相编码有两种颜色，即两种颜色。数据定义为“奇”和“偶”，通过交替传输不同颜色的码字来检测不同的有效数据。在该协议中，接收器和发送器发送颜色信息作为请求信号，然后发送数据。传输由检测相互的颜色信息是否相同由于两个请求信号可以同时发送，因此可以进行重叠通信，因为在异步数据传输中数据和颜色信息必须捆绑在同一根线上，因此检测很重要。来自数据和颜色信息的混合双轨代码的有效数据的使用使得通过计算码字之和可以轻松地合并和检测数据和颜色信息。因为电流模式线性求和可以由于无需任何有源器件，可以通过布线来实现，因此所提出的异步电路变得简单，而且，来自两侧的电流信号可以叠加在同一条线上，这是多值电流模式逻辑实现控制信号复用的重要特征。使用带有读出放大器的比较器可以轻松快速地检测码字分量的总和。事实上，在 0.18um CMOS 技术中评估了所提出的异步数据传输方案的数据传输周期。在标准化功耗较小的情况下，多值电流模式逻辑电路的速度比相应的二进制 CMOS 实现快约 1.5 倍。