Implementation of a High-Performance Multiple-Valued Current-Mode VLSI System with Low-Power and Highly Reliable Capabilities

具有低功耗和高可靠性功能的高性能多值电流模式 VLSI 系统的实现

基本信息

批准号：
12680324
负责人：
HANYU Takahiro
金额：
$ 2.37万
依托单位：
Tohoku University
依托单位国家：
日本
项目类别：
Grant-in-Aid for Scientific Research (C)
财政年份：
2000
资助国家：
日本
起止时间：
2000 至 2002
项目状态：
已结题

项目摘要

Low-power circuit design while maintaining a high-speed capability is needed not only for battery-powered portable applications but also to reduce the power dissipation of dedicated apecial-purpose VLSI processors, because the extra current density in interconnections causes temporal or permanent malfunction due to voltage drops or electromigrations. Multiple-valued current-mode (MVCM) integrated circuits have a potential advantage to reduce the wiring complexity and the nurnber of active devices in arithmetic large-scale-integration chips because the frequently used linear sum operation can be performed simply by wiring with no active devices. However, the switching speed in the MVCM circuit is relatively slow, and its power dissipation due to the steady current becomes high because current-sources in differential-pair circuits always flow a constant current in the active mode. In this project, a new MVCM circuit based on dual-rail differential logic has been proposed for high-speed, … More low-power, highly reliable arithmetic-oriented VLSI. A differential logic-style circuit has an attractive feature that its input voltage swing is small enough while maintaining a high currentdriving capability. The combination of the differential logic style and MVCM circuitry in arithmetic VLSI makes it possible to improve the switching speed compared with that of a corresponding binary CMOS implementation. Moreover, the use of a precharge-evaluate logic style abo makes the steady current flow cut off, which results in great reduction of dynamic power dissipation. A judicious combination of differential logic, MVCM logic and dynamic logic in the proposed circuit makes it possible to reduce the power dissipation together with device and interconnection counts while maintaining a high-speed switching capability. The use of dual-rail coding, which is used in differential logic-style circuit, is a widely used encoding style of asynchronous and self-checking circuit implementation. From this point of view, we have also proposed high-performance asynchronous and self-checking circuit using multiple-valued dual-rail complementary signals. Less

在保持高速功能的同时，低功率电路设计不仅需要用于电池供电的便携式应用程序，而且还需要减少专用的Apecial-Purpose VLSI处理器的功率耗散，因为互连中的额外电流密度会导致临时或由于电压下降或电子迁移而引起的临时或永久性故障。多价值电流模式（MVCM）集成电路具有潜在的优势，可以降低算术大规模整合芯片中的接线复杂性和主动设备的护士，因为可以简单地通过无活动设备接线来执行经常使用的线性总和操作。但是，MVCM电路中的开关速度相对较慢，并且由于电流稳定电流引起的功率耗散，因为差速器电路中的电流始终在活动模式下流动恒定电流。在这个项目中，已经提出了一个基于双轨差异逻辑的新的MVCM电路，用于高速，……更低功率，高度可靠的面向算术的VLSI。差异逻辑风格的电路具有吸引人的功能，其输入电压摆动足够小，同时保持高电流驱动能力。与相应的二进制CMOS实现相比，算术VLSI中差异逻辑样式和MVCM电路的组合使得可以提高开关速度。此外，使用预声处理的逻辑样式ABO会导致稳定的电流切断，从而大大降低了动态功率耗散。拟议电路中差分逻辑，MVCM逻辑和动态逻辑的明智组合使与设备和互连计数一起减少功率耗散是可能的，同时保持高速开关功能。在差异逻辑风格电路中使用的双轨编码是一种广泛使用的编码样式的异步和自我检查电路实现。从这个角度来看，我们还提出了使用多价值双轨完全信号的高性能异步和自我检查电路。较少的