Realization of a high speed hardware compile engine for multiple languages

多语言高速硬件编译引擎的实现

基本信息

批准号：
61850061
负责人：
ITANO Kozo
金额：
$ 12.8万
依托单位：
University of Tsukuba
依托单位国家：
日本
项目类别：
Grant-in-Aid for Developmental Scientific Research
财政年份：
1986
资助国家：
日本
起止时间：
1986 至 1988
项目状态：
已结题

项目摘要

In order to execute a program at high speed, compilation is a very important process which transforms the source program into machine codes with optimization. However, the compilation takes a very large amount of the processing time of the computer in the program development system. This tendency is higher for the reseach and educational uses. This situation implies that we can increase the system performance by reducing compiling time, seperating it as a independent hardware unit from the host processor. Our reseach objective is to realize a hardware compile engine which can compile a source program very fast, e.g several ten times faster. Current complier implementation technology seems to be enough matured on software basis. Therefore, we analyzed these technology whether they are matched with hardware realization. On haredware dasis, detailed parallel processing is easily incorporated for speed-up. High speed table search can accelerate the processing speed. Some technolygy has been imported from the direct-execution computer of our preceding project. The design principles of the hardware complier is (1) language flexibility, (2) high-speed execution, and (3) modular design. Actually, the entire hardware is devided into four functional units: lexical unit, parsing unit, semantic unit, and code generator. These units are connnected in pipeline, and operated in parallel. The basic design of the lexical unit is inherited from that of the diret-execution computer, but simpified and a little bit slowed. The parser is designed on LR(1) basis which basically accepts the YACC parsing table. For the sematic analyzer, parallel analysis is to solve the buttle neck of the pipeline.

为了高速执行程序，编译是一个非常重要的过程，它将源程序转换为具有优化的机器代码。但是，该汇编需要计算机开发系统中计算机的大量处理时间。对于研究和教育用途而言，这种趋势更高。这种情况意味着我们可以通过减少编译时间来增加系统性能，从而将其作为独立硬件单元与主机处理器分开。我们的调整目标是实现硬件编译引擎，该硬件可以很快地编译源程序，例如，几次更快。当前的合格实施技术似乎已经足够成熟。因此，我们分析了这些技术是否与硬件实现相匹配。在Haredware Dasis上，详细的并行处理很容易合并以加速。高速桌搜索可以加速处理速度。已经从我们先前项目的直接执行计算机中进口了一些技术。硬件符合者的设计原理是（1）语言灵活性，（2）高速执行和（3）模块化设计。实际上，整个硬件分为四个功能单元：词汇单元，解析单元，语义单元和代码生成器。这些单元在管道中被固定，并并行操作。词汇单元的基本设计是从Diret执行计算机的基本设计中继承的，但含糊不清，有点放慢。解析器的设计基本上接受YACC解析表。对于半分析仪，平行分析是解决管道的凝结颈。