CAREER: Next Generation of High-Level Synthesis for Agile Architectural Design (ArchHLS)

职业:下一代敏捷架构设计高级综合 (ArchHLS)

基本信息

  • 批准号:
    2338365
  • 负责人:
  • 金额:
    $ 56万
  • 依托单位:
  • 依托单位国家:
    美国
  • 项目类别:
    Continuing Grant
  • 财政年份:
    2024
  • 资助国家:
    美国
  • 起止时间:
    2024-06-01 至 2029-05-31
  • 项目状态:
    未结题

项目摘要

In the landscape of computing, the demand for innovative hardware architectures is ever-growing, driving advancements in computer architecture. However, the conventional Register Transfer Level (RTL) design approach is time-consuming and labor-intensive. This project aims to facilitate the broader adoption of High-Level Synthesis (HLS) tools to significantly reduce design time, particularly for general architectural design. HLS tools enable higher-level programming and automatic synthesis, yet their application in comprehensive computer architecture studies remains limited. The significance of this project lies in promoting agile hardware development by fundamentally innovating HLS tools, overcoming the productivity challenges at the register transfer level, and unlocking the potential for more widespread application of HLS in diverse computing domains. The developed tool chain will be publicly available and exposed to more users by organizing tutorials, workshops, and demo events. The research will be integrated into education programs with activities on research training for undergraduate and master students, including online students, recruitment and retention of students from underrepresented groups, curriculum development, and innovative international design competitions co-hosted with industry.This project aims to revolutionize High-Level Synthesis (HLS) tools by introducing a next-generation tool, ArchHLS, addressing two major research challenges. First, HLS tools are superior in synthesizing a specific algorithm into hardware but have limited capability for general domain-specific architecture designs. Second, it is challenging to design general architectures with compatible compilers and to automatically improve the underlying architecture for evolving workloads. To address these challenges, ArchHLS facilitates agile hardware development by making three key innovations. First, ArchHLS decouples architectural design and workload mapping, allowing flexible architecture extraction and customized control flow. Second, ArchHLS automates architecture evolution to adapt to fast-changing algorithms via automated workload compilation, mapping, and computation pattern matching. Third, ArchHLS enables comprehensive and accurate performance profiling for designs to provide feedback for architecture evolution. Beyond advancing Electronic Design Automation (EDA) tooling, this research has broader societal implications, aligning with the grand vision of sustainability for computing and computing for sustainability, such as climate modeling and scientific computing. The public availability of the toolchain fosters research dissemination, educational integration, and inclusivity efforts, aiming to benefit diverse communities and promote efficient algorithm/architecture co-design.This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.
在计算的景观中,对创新硬件体系结构的需求正在不断增长,推动了计算机体系结构的进步。但是,常规的寄存器转移级别(RTL)设计方法是耗时且劳动力密集的。该项目旨在促进更广泛地采用高级合成(HLS)工具,以大大减少设计时间,尤其是对于一般的建筑设计。 HLS工具可实现高级编程和自动合成,但它们在综合计算机架构研究中的应用仍然有限。该项目的重要性在于通过从根本上创新HLS工具,克服寄存器转移级别的生产力挑战,并释放了在不同的计算域中更广泛应用的潜力,从而促进了敏捷硬件开发。开发的工具链将公开使用,并通过组织教程,研讨会和演示活动向更多用户接触。这项研究将通过针对本科生和硕士学生进行研究培训的活动纳入教育计划,包括在线学生,招聘和保留来自代表性不足的小组,课程发展以及与行业共同主持的创新国际设计竞赛的学生。该项目旨在通过对高级合成(HLS)进行彻底介绍下一个挑战工具,以彻底介绍下一个挑战工具,以彻底介绍两次挑战工具。首先,HLS工具在将特定算法合成到硬件中的合成方面是优越的,但是对于一般域特异性体系结构设计的功能有限。其次,设计具有兼容编译器的通用体系结构并自动改善不断发展的工作负载的基础体系结构是一项挑战。为了应对这些挑战,ARDHLS通过进行三个关键创新来促进敏捷硬件的开发。首先,ARDHLS将建筑设计和工作负载映射解开,从而可以灵活地提取和自定义的控制流。其次,Archhls自动化体系结构的演变,以通过自动化工作负载编译,映射和计算模式匹配来适应快速变化的算法。第三,ARDHLS可以为设计提供全面,准确的性能分析,以提供建筑演化的反馈。除了推进电子设计自动化(EDA)工具外,这项研究还具有更广泛的社会含义,与可持续性的计算和计算可持续性的宏伟愿景一致,例如气候建模和科学计算。工具链的公众可用性促进了研究传播,教育融合和包容性努力,旨在使多元化社区受益并促进有效的算法/建筑联合设计。该奖项反映了NSF的法定任务,并被认为是通过基金会的知识分子功能和广泛的影响来评估Criteria的评估。

项目成果

期刊论文数量(0)
专著数量(0)
科研奖励数量(0)
会议论文数量(0)
专利数量(0)

暂无数据

数据更新时间:2024-06-01

Cong Hao其他文献

3D-IC signal TSV assignment for thermal and wirelength optimization
用于热和线长优化的 3D-IC 信号 TSV 分配
Interconnection Allocation Between Functional Units and Registers in High-Level Synthesis
高级综合中功能单元和寄存器之间的互连分配
TSV Assignment of Thermal and Wirelength Optimization for 3D-IC Routing
3D-IC 布线的热和线长优化的 TSV 分配
Economical Smart Home Scheduling for Single and Multiple Users
针对单个和多个用户的经济智能家居调度
  • DOI:
  • 发表时间:
    2016
    2016
  • 期刊:
  • 影响因子:
    0
  • 作者:
    Cong Hao;Takeshi Yoshimura
    Cong Hao;Takeshi Yoshimura
  • 通讯作者:
    Takeshi Yoshimura
    Takeshi Yoshimura
An Efficient Algorithm for 3D-IC TSV Assignment
3D-IC TSV 分配的高效算法
  • DOI:
  • 发表时间:
    2016
    2016
  • 期刊:
  • 影响因子:
    0
  • 作者:
    Cong Hao;Nan Ding;Takeshi Yoshimura
    Cong Hao;Nan Ding;Takeshi Yoshimura
  • 通讯作者:
    Takeshi Yoshimura
    Takeshi Yoshimura
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Cong Hao的其他基金

CSR: Small: Multi-FPGA System for Real-time Fraud Detection with Large-scale Dynamic Graphs
CSR:小型:利用大规模动态图进行实时欺诈检测的多 FPGA 系统
  • 批准号:
    2317251
    2317251
  • 财政年份:
    2024
  • 资助金额:
    $ 56万
    $ 56万
  • 项目类别:
    Standard Grant
    Standard Grant
Machine Learning-assisted Modeling and Design of Approximate Computing with Generalizability and Interpretability
具有通用性和可解释性的机器学习辅助建模和近似计算设计
  • 批准号:
    2202329
    2202329
  • 财政年份:
    2022
  • 资助金额:
    $ 56万
    $ 56万
  • 项目类别:
    Standard Grant
    Standard Grant

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