CSR: Small: Cache-Coherent Accelerators for Efficient Persistent Memory Programming

CSR：小型：用于高效持久内存编程的缓存一致性加速器

• 批准号: 2245999
• 负责人: Ryan Stutsman
• 金额: $ 59.29万
• 依托单位: University of Utah
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 2023
• 资助国家: 美国
• 起止时间: 2023-10-01 至 2026-09-30
• 项目状态: 未结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=2245999&HistoricalAwards=false
• 关键词: CSR; Small; Cache; Coherent; Accelerators

Persistent memory (PM) is a new class of computer storage that upends the model that computer systems have used for more than half a century. Unlike conventional storage devices, PM can be accessed by CPUs as if it were memory. Accessing storage this way can be implemented in hardware instead of software, so it can be accessed more quickly and efficiently than conventional storage devices. Even so, it persists across faults and power failures. This proposal seeks to convert existing software to use this faster PM-based storage without requiring programmers to change their code while providing safety during crashes and power failures. Unlike existing approaches, the proposed approach does this using emerging commercially available hardware; hence, it is fast and efficient since it does not reintroduce software to the CPU storage access path.The improved computer system memory performance, efficiency, and capacity that PM provides when combined with this project's accelerated crash consistency will have broad benefits to many private and public sector applications. Many of the costs that virtually all database systems introduce to survive crashes and power failures can be mitigated by the proposed approach. Furthermore, applications that process and modify massive data sets in real-time including data center applications, social networks, and machine learning training and inference over changing data sets can all benefit from improved scale, performance, and efficiency. Hence, this work can help accelerate code in the data center applications that are used by billions of users daily.This project will also carry out several outreach and educational activities along with specific collaborations to encourage industry adoption including a tutorial, a new graduate seminar, new modules for graduate and undergraduate courses, and a new course lab assignment. Additionally, the PI will host two incoming undergraduate students from an underrepresented group for research rotations as well as host two undergraduates through the NSF REU program. The resulting tools, framework, and accelerator code will be developed in the open under a permissive license to support use and development both in academia and industry, and it will be packaged for easy use and deployment on open platforms.In more detail, PM support in recent CPU architectures allows CPUs to access and manipulate massive data sets, lowering data access times from 10s of microseconds to 100s of nanoseconds. However, system crashes in the middle of modifying persistent data structures can lead to inconsistencies that are difficult or impossible to repair; thus, today PM-based data structures still place software on the path to storage access to provide extra steps for crash consistency. The key insight of this proposal is that the interposition needed on PM data accesses for crash consistency can be done fully in hardware without any changes to existing CPU architectures by using newly emerging cache-coherent accelerators and field-programmable gate arrays (FPGAs). Furthermore, it can be done with existing, off-the-shelf code for data structures that were designed without PM in mind. In the proposed approach, applications interact with PM through a hardware FPGA, which carefully controls how changes are propagated to PM to provide crash consistency. Since this interposition is in hardware it is efficient, which helps realize the full performance potential of PM's direct load/store interface. Also, this new approach works well with CPUs' cache coherence protocols, so CPUs can cache PM data more aggressively than is safe with direct PM access; in turn, this makes the proposed approach faster than direct load/store access to PM in many cases. Finally, the proposed work includes using this cache-coherent accelerator to provide replicated, fault-tolerant PM, and it includes new approaches to hiding PM and remote memory access times by implementing new, intelligent prefetching policies in hardware without CPU changes.This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.

持久内存 (PM) 是一种新型计算机存储，它颠覆了计算机系统半个多世纪以来使用的模型。与传统存储设备不同，PM 可以像内存一样被 CPU 访问。这种方式访问​​存储可以用硬件而不是软件来实现，因此可以比传统存储设备更快速、更高效地访问。即便如此，它在出现故障和电源故障时仍然存在。该提案旨在将现有软件转换为使用这种更快的基于 PM 的存储，而不需要程序员更改其代码，同时在崩溃和电源故障期间提供安全性。与现有方法不同，所提出的方法使用新兴的商用硬件来实现这一点；因此，它快速高效，因为它不会将软件重新引入 CPU 存储访问路径。PM 提供的改进的计算机系统内存性能、效率和容量与该项目的加速崩溃一致性相结合，将为许多私人和企业带来广泛的好处。公共部门应用。几乎所有数据库系统在崩溃和电源故障时所产生的许多成本都可以通过所提出的方法来减轻。此外，实时处理和修改海量数据集的应用程序（包括数据中心应用程序、社交网络以及机器学习训练和对不断变化的数据集进行推理）都可以从规模、性能和效率的提高中受益。因此，这项工作可以帮助加速数十亿用户每天使用的数据中心应用程序中的代码。该项目还将开展多项外展和教育活动以及具体合作，以鼓励行业采用，包括教程、新的研究生研讨会、研究生和本科生课程的新模块以及新的课程实验室作业。此外，PI 将接待来自代表性不足群体的两名即将入学的本科生进行研究轮换，并通过 NSF REU 项目接待两名本科生。由此产生的工具、框架和加速器代码将在许可下公开开发，以支持学术界和工业界的使用和开发，并将打包以便在开放平台上轻松使用和部署。更详细地说，PM 支持最新的 CPU 架构允许 CPU 访问和操作海量数据集，将数据访问时间从数十微秒降低到数百纳秒。然而，在修改持久数据结构过程中系统崩溃可能会导致难以或无法修复的不一致；因此，今天基于 PM 的数据结构仍然将软件置于存储访问路径上，以提供额外的步骤来实现崩溃一致性。该提案的关键见解是，通过使用新兴的缓存一致性加速器和现场可编程门阵列 (FPGA)，可以完全在硬件中完成 PM 数据访问所需的插入以实现崩溃一致性，而无需对现有 CPU 架构进行任何更改。此外，它可以使用现有的、现成的数据结构代码来完成，这些代码在设计时没有考虑 PM。在所提出的方法中，应用程序通过硬件 FPGA 与 PM 交互，硬件 FPGA 仔细控制更改如何传播到 PM 以提供崩溃一致性。由于这种插入是在硬件中进行的，因此非常高效，这有助于充分发挥 PM 直接加载/存储接口的性能潜力。此外，这种新方法与 CPU 的缓存一致性协议配合良好，因此 CPU 可以比直接 PM 访问更安全地缓存 PM 数据；反过来，在许多情况下，这使得所提出的方法比直接加载/存储访问 PM 更快。最后，拟议的工作包括使用这种缓存一致性加速器来提供复制的、容错的 PM，并且它包括通过在硬件中实施新的智能预取策略而无需更改 CPU 来隐藏 PM 和远程内存访问时间的新方法。该奖项反映了通过使用基金会的智力价值和更广泛的影响审查标准进行评估，NSF 的法定使命被认为值得支持。