FuSe-TG: The Future of Semiconductor Technologies for Computing through Device-Architecture-Application Co-Design

FuSe-TG：通过设备-架构-应用协同设计进行计算的半导体技术的未来

• 批准号: 2235329
• 负责人: Subhasish Mitra
• 金额: $ 29.96万
• 依托单位: Stanford University
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 2023
• 资助国家: 美国
• 起止时间: 2023-05-01 至 2025-04-30
• 项目状态: 未结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=2235329&HistoricalAwards=false
• 关键词: FuSe; TG; Future; Semiconductor; Technologies; FuSe; TG; Future; Semiconductor; Technologies

A 2020 issue of Massachusetts Institute of Technology’s Tech Review read “[Moore’s law] has fueled prosperity of the last 50 years. But the end is now in sight.” However, this latter conclusion can be debated. Historically, exponential growth in semiconductors was achieved through two-dimensional (2D) miniaturization of devices (transistors, memory, and wires) to pack more components in the same chip area and achieve lower cost per function. Indeed, we are now reaching the physical limits of this 2D scaling paradigm. However, alternative approaches will trigger a seismic shift to reinvigorate the US semiconductor economy. This project will explore, identify, and map out the possible paths that lie ahead through partnerships among universities and industry/industrial research leaders in semiconductors, through educational efforts to translate new knowledge into the educational pipeline and semiconductor workforce, and through piloting new collaboration methods to enable lab-to-fab translation more readily with robust inputs from industry experts. This teaming grant will thus break new grounds for the future of semiconductors for domain-specific computing. The longer-term goal is to create national impact on research, education, and commercialization by encouraging students to follow a career path in semiconductors near national fab facilities. This is planned through multiple catalysts, e.g., a pilot program for lab and fab experiences for community college students, co-design challenges etc.In the past two decades, it has become increasingly untenable to create architectures and device technologies independent of one another because there are intertwined dependencies across the abstraction boundaries. In addition, because of the extreme energy efficiency demands of future systems, architectures and device technologies must be driven by the specific application domains at hand. Thus, the focus of this project is device-architecture-application co-design. Building in the third dimension (3D, like a high-rise), with ultra-dense vertical connectivity between 3D layers, could significantly increase the number of devices packed on a piece of chip real estate in a scalable manner for significant benefits in energy and throughput, as, e.g., used by the Stanford Nano-Engineered Computing Systems Technology (N3XT) 3D approach. Multiple N3XT 3D chips are to be integrated through a continuum of chip stacking-/interposer-/wafer-level assembly/ integration. The foundation for this teaming activities will be the MOnolithic Stacked, Assembled IC (MOSAIC) N3XT 3D concept. Rather than relying solely on silicon-based transistors to perform all desired functions, heterogeneous materials and customized device structures optimally designed to perform diverse/distinct functions, i.e., domain-specific device technologies, will be used. The project will explore new domain-specific architectures (e.g., targeting AI deep neural nets, augmented reality/virtual reality, and graph analytics) uniquely enabled by the technology concepts, new Electronic Design Automation tools, and new open-source frameworks for device-architecture-application co-design.This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.

2020年的马萨诸塞州理工学院的技术评论上写道：“ [摩尔定律]在过去50年中促进了繁荣。但是现在已经看到了结局。”但是，以后的结论可以辩论。从历史上看，半导体的指数增长是通过对设备（晶体管，内存和电线）的二维（2D）微型化来实现的，以在同一芯片区域包装更多组件并实现较低的每个功能成本。确实，我们现在达到了这个2D缩放范式的物理极限。但是，替代方法将引发地震转变，以振兴美国半导体经济。该项目将通过教育努力将新知识转化为教育管道和半导体劳动力，并通过实行新的合作方法来探索，识别和绘制通过大学，行业/工业研究领导者之间的合作伙伴关系的可能道路，并通过将新知识转化为教育管道和半导体的劳动力。因此，该组合赠款将为特定于域的计算的半导体的未来打破新的理由。长期的目标是通过鼓励学生遵循国家晶圆厂设施附近半导体的职业道路来对研究，教育和商业化产生全国影响。这是通过多个催化剂计划的，例如，针对社区大学生的实验室和FAB体验，共同设计挑战等的试点计划，在过去的二十年中，创建彼此独立于彼此的建筑和设备技术变得越来越站不住脚，因为在抽象范围内存在相互交织的依赖。此外，由于未来系统的极端能源效率需求，架构和设备技术必须由当前的特定应用程序域驱动。这是该项目的重点是设备 - 架构应用程序共同设计。建立在第三维（3D，例如高层）中，具有3D层之间具有超密集的垂直连接性，可以显着增加芯片房地产上包装的设备的数量，以可扩展的方式填充一块芯片房地产的设备，从而在能源和吞吐量中具有重大好处，例如，斯坦福纳米工程式的计算系统技术（N3XT）使用了斯坦福大学纳米工程技术技术（N3XT）3D方法。多个N3XT 3D芯片将通过芯片堆叠 - /interposer-/w​​afer级装配/集成的连续集成。这项团队活动的基础将是整体堆积的，组装的IC（Mosaic）N3XT 3D概念。与其仅依靠基于硅的变压器来执行所有所需的功能，异质材料和最佳设计用于执行潜水员/不同功能的定制设备结构，即使用特定于域的设备技术。该项目将探索新的特定领域特定体系结构（例如，针对AI深神经网，增强现实/虚拟现实和图形分析），由技术概念，新的电子设计自动化工具，新的电子设计自动化工具以及新的开放源代码框架来启用，并通过对设备实现的授权进行评估。智力优点和更广泛的影响审查标准。