CRII: SHF: Error Resilient Asynchronous Architecture for Ultra-Low Power Energy Harvesting IoT Applications

CRII：SHF：适用于超低功耗能量收集物联网应用的容错异步架构

基本信息

批准号：
2153373
负责人：
Ashiq Sakib
金额：
$ 17.5万
依托单位：
Florida Polytechnic University
依托单位国家：
美国
项目类别：
Standard Grant
财政年份：
2022
资助国家：
美国
起止时间：
2022-03-01 至 2025-02-28
项目状态：
未结题

来源：
https://www.nsf.gov/awardsearch/showAward?AWD_ID=2153373&HistoricalAwards=false
关键词：
CRII SHF Error Resilient Asynchronous

项目摘要

This award is funded in whole or in part under the American Rescue Plan Act of 2021 (Public Law 117-2).As the demand for self-powered smart electronics and battery-less solutions increases, energy harvesting will be the power source of the future. Energy-harvesting devices operate on energy derived from ambient environmental sources or human activities. However, due to the limited energy density and irregular energy profile of different energy sources, such self-powered devices should be extremely energy-efficient and functional even under fluctuating supply voltages. Nowadays, most devices based on conventional synchronous (clocked) digital designs are extremely power-hungry, with the clock accounting for a significantly large portion of the consumed energy. Moreover, device miniaturization results in major design challenges, which makes clocked designs more susceptible to supply-voltage variations and unsuitable for devices operating on harvested energy. Asynchronous (clockless) designs can resolve the power inefficiencies associated with clocked designs, and have the potential to bring a whole class of applications into the domain serviceable by energy harvesting. With this vision, the primary objective of this project is to design error-resilient asynchronous circuits, which can create a venue to implement robust, unsupervised, maintenance-free, safe, sustainable, and low-power electronics for numerous energy harvesting-powered applications in different sectors, such as medical, space, defense, automobile, power industry, etc.The goal of this project is to develop a robust, reliable, and error-tolerant Quasi Delay Insensitive (QDI) asynchronous architecture for ultra-low power applications, which can perform energy-efficient computation and provide protection against radiation-induced transient errors in unsupervised scenarios. While numerous error-detection and -mitigation techniques exist for synchronous designs, there are very few for QDI asynchronous circuits. Also, the existing methods have major limitations, such as failure to ensure complete resilience, failure to halt error propagation in QDI pipelines, failure to circumvent duplication resulting in latency, energy, and area overhead, etc. This project aims to address these limitations by conducting research in two phases. The first phase will focus on 1) systematically analyzing the error response of QDI asynchronous circuits, and 2) developing a scalable and efficient formal framework to identify vulnerable components in both the data path and control path. The second phase will leverage the framework developed in the first phase to 1) critically analyze the vulnerable components and critical paths, 2) investigate possible architectural modifications for complete error-resilience, 3) ensure proper actions to prevent fault propagation through the QDI pipeline, and 4) perform cost/performance trade-off analysis of the newly developed architecture.This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.

该奖项的全部或部分资金根据《2021 年美国救援计划法案》（公法 117-2）提供。随着对自供电智能电子产品和无电池解决方案的需求增加，能量收集将成为未来。能量收集设备利用来自周围环境来源或人类活动的能量进行操作。然而，由于不同能源的能量密度有限且能量分布不规则，这种自供电设备即使在电源电压波动的情况下也应该具有极高的能效和功能。如今，大多数基于传统同步（时钟）数字设计的设备都非常耗电，其中时钟占据了消耗能源的很大一部分。此外，设备小型化带来了重大的设计挑战，这使得时钟设计更容易受到电源电压变化的影响，并且不适合依靠收集的能量运行的设备。异步（无时钟）设计可以解决与时钟设计相关的电源效率低下问题，并有可能将整类应用带入可通过能量收集进行服务的领域。秉持这一愿景，该项目的主要目标是设计抗错误异步电路，为众多能量收集供电应用提供稳健、无监督、免维护、安全、可持续和低功耗电子产品的场所该项目的目标是为超低功耗应用开发强大、可靠且容错的准延迟不敏感（QDI）异步架构，可以执行节能计算，并在无人监督的情况下提供针对辐射引起的瞬态错误的保护。虽然同步设计存在多种错误检测和缓解技术，但 QDI 异步电路的错误检测和缓解技术却很少。此外，现有方法存在重大局限性，例如无法确保完全弹性、无法阻止 QDI 管道中的错误传播、无法避免导致延迟、能源和面积开销的重复等。该项目旨在通过以下方式解决这些限制：分两个阶段进行研究。第一阶段将重点关注 1) 系统分析 QDI 异步电路的错误响应，2) 开发可扩展且高效的形式框架，以识别数据路径和控制路径中的易受攻击的组件。第二阶段将利用第一阶段开发的框架来 1) 批判性地分析易受攻击的组件和关键路径，2) 研究可能的架构修改以实现完全的容错能力，3) 确保采取适当的措施来防止故障通过 QDI 管道传播， 4) 对新开发的架构进行成本/性能权衡分析。该奖项反映了 NSF 的法定使命，并通过使用基金会的智力优点和更广泛的影响审查标准进行评估，被认为值得支持。