SHF: Small: Leveraging Monolithic 3D for Architectural Innovations

SHF：小型：利用整体 3D 进行建筑创新

• 批准号: 2008365
• 负责人: VIJAYKRISHNAN NARAYANAN
• 金额: $ 50万
• 依托单位: Pennsylvania State Univ University Park
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 2020
• 资助国家: 美国
• 起止时间: 2020-06-15 至 2024-05-31
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=2008365&HistoricalAwards=false
• 关键词: SHF; Small; Leveraging; Monolithic; 3D; SHF; Small; Leveraging; Monolithic; 3D

The design of more efficient processors is a major driving force of the computing industry. Over multiple decades, reducing the size of transistors, which are the building blocks of microprocessors, has been the main driver for efficiency improvements. With this trend of transistor shrinking nearing the physical limit, this research explores three-dimensional chips, where transistors are stacked in multiple layers, as an alternate approach to enhance efficiency. A major challenge with three-dimensional chips is the large dimension of the connections compared to the transistor itself. This project will leverage a new technology called monolithic three-dimensional design (M3D), where inter-layer connections are of dimensions similar to that of a transistor. This research will result in new M3D-based designs for microprocessors that reduce energy and time consumed in interconnections, and enable new functional features for microprocessors. The project will also enhance the national workforce development efforts by training undergraduate, graduate and underrepresented groups in a much-needed area of semiconductor electronics. This project will involve synergistic exploration of process technology and M3D-based architectural design spaces of processors towards achieving transformational impact on processor and accelerator performance. The research will first develop a simulation infrastructure that enables systematic exploration of the space by varying the architectural and technology parameters. Leveraging the simulation infrastructure, this project will perform the following tasks: (1) evaluation of layer-wise partitioning of processor core and cache structures; (2) design of primitive compute functions for integration with the cache memories; (3) design of M3D-enabled application-specific accelerators; and (4) integration of heterogeneous memory technologies to provide support for power efficiency.This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.

更有效的处理器的设计是计算行业的主要推动力。在数十年中，减少晶体管的大小（这是微处理器的基础）一直是提高效率的主要驱动力。随着这种晶体管收缩接近物理极限的趋势，这项研究探索了三维芯片，其中将晶体管堆叠成多层，作为提高效率的另一种方法。三维芯片的主要挑战是与晶体管本身相比，连接的巨大维度。该项目将利用一种称为单层的三维设计（M3D）的新技术，其中层间连接的维度与晶体管相似。这项研究将为微处理器提供新的基于M3D的设计，以减少互连中的能量和时间，并为微处理器提供新的功能功能。该项目还将通过急需的半导体电子领域的培训本科，研究生和代表性不足的群体来改善国家劳动力发展工作。该项目将涉及对过程技术和基于M3D的处理器的协同探索，以实现对处理器和加速器性能的变革影响。该研究将首先开发一个模拟基础架构，该基础架构可以通过改变建筑和技术参数来实现对空间的系统探索。利用仿真基础架构，该项目将执行以下任务：（1）评估处理器核心和高速缓存结构的层划分； （2）设计原始计算函数，以与缓存记忆集成； （3）设计启用M3D的应用程序特定加速器； （4）将异构记忆技术的整合以提供对功率效率的支持。该奖项反映了NSF的法定任务，并使用基金会的知识分子优点和更广泛的影响审查标准，被认为值得通过评估来获得支持。