FeFET-Based Logic-in-Memory Supporting SA-Free Write-Back and Fully Dynamic Access With Reduced Bitline Charging Activity and Recycled Bitline Charge

Bitwise logic-in-memory (BLiM) is a promising approach to efficient computing in data-intensive applications by reducing data movement between memory and processing units. However, existing BLiM techniques have challenges towards higher energy efficiency and speed: (i) DC power in computing and result sensing is significant in most existing RRAM and MRAM based BLiM solutions; (ii) before the computation result could be stored back to the same memory array, existing BLiM has to sense the result first, at the cost of extra power and latency due to the sense amplifiers (SAs). Targeting at higher energy efficiency and speed, this work proposes a new BLiM approach in 2-transistor/ cell (2T/C) and 3T/C topologies based on ferroelectric field-effect transistors (FeFETs), supporting a variety of computing functions. For the first time, this new approach supports SA-free direct write-back, and consumes no static power for computing and sensing with proposed fully dynamic computing and sensing schemes. Another highlight is that this work further minimizes the dynamic power by (i) reducing the chance of bitline charging activities and (ii) recycling the bitline charge in sensing multi-operand operations. Compared with prior BLiM methods based on nonvolatile memories, evaluation shows 3.0x–100x latency and 1.3x–200x energy improvement for typical in- memory XOR operation, which further leads to 3.0x–58x and 3.2x–78x savings of latency and energy, respectively, for the application of advanced-encryption standard (AES).

位逻辑内存中计算（BLiM）是一种在数据密集型应用中通过减少内存和处理单元之间的数据移动来实现高效计算的有前途的方法。然而，现有的BLiM技术在提高能效和速度方面面临挑战：（i）在大多数现有的基于阻变随机存取存储器（RRAM）和磁随机存取存储器（MRAM）的BLiM解决方案中，计算和结果检测中的直流功耗显著；（ii）在计算结果能够被存储回同一存储阵列之前，现有的BLiM必须首先检测结果，由于检测放大器（SAs），这会消耗额外的功率并产生延迟。针对更高的能效和速度，这项工作提出了一种基于铁电场效应晶体管（FeFET）的2晶体管/单元（2T/C）和3T/C拓扑结构的新型BLiM方法，支持多种计算功能。这种新方法首次支持无检测放大器的直接写回，并且通过提出的全动态计算和检测方案，在计算和检测过程中不消耗静态功率。另一个亮点是，这项工作通过（i）减少位线充电活动的几率和（ii）在检测多操作数操作中回收位线电荷，进一步将动态功率降至最低。与基于非易失性存储器的先前BLiM方法相比，评估表明，对于典型的内存中异或操作，延迟提高了3.0倍 - 100倍，能耗提高了1.3倍 - 200倍，这进一步使得高级加密标准（AES）应用的延迟和能耗分别节省了3.0倍 - 58倍和3.2倍 - 78倍。