On the Write Schemes and Efficiency of FeFET 1T NOR Array for Embedded Nonvolatile Memory and Beyond

Ferroelectric field-effect-transistor ( FeFET) 1T NOR Array is promising for multiple applications yet not well studied on its write mechanism and schemes. In this work, we demonstrate: i) A comprehensive model which reflects two FeFET write mechanisms - one to ground Source (S), Drain (D) & Body (B) nodes and use Gate (G) to write, and the other to float S/D and use G & B to write; ii) 3 write schemes for conventional FeFET 1T NOR arrays and another one for the diagonal array, the latter of which shows the advantages of low write energy and high write efficiency but with the penalty area cost; iii) A study of parasitic parameters, particularly gate resistance (R-g), gate capacitance (C-g) and word line resistance (R-WL), in FeFET 1T NOR array, which is critical for further prospective 1T NOR array design; iv) An implementation of FeFET 1T NOR array in the Ising machine system to evaluate the feasibility of our write scheme and array structure for embedded nonvolatile memory (NVM) applications.

铁电场效应晶体管（FeFET）1T NOR阵列在多种应用领域颇具潜力，然而其写入机制和方案尚未得到充分研究。在本研究中，我们展示了： i) 一个综合模型，该模型反映了两种FeFET写入机制——一种是将源极（S）、漏极（D）和体极（B）节点接地，通过栅极（G）进行写入；另一种是使源极/漏极浮空，通过栅极和体极进行写入； ii) 针对传统FeFET 1T NOR阵列的3种写入方案，以及针对对角阵列的另一种写入方案，后者展现出写入能量低和写入效率高的优势，但代价是面积成本增加； iii) 对FeFET 1T NOR阵列中寄生参数的研究，特别是栅极电阻（R - g）、栅极电容（C - g）和字线电阻（R - WL），这对于未来1T NOR阵列的进一步设计至关重要； iv) 在伊辛机系统中实现FeFET 1T NOR阵列，以评估我们的写入方案和阵列结构在嵌入式非易失性存储器（NVM）应用中的可行性。