CRII: SHF: Synthesis of Near-Tree Clock Networks with No Short Circuit Current that Can be Reconfigured into a Tree Topology

CRII：SHF：无短路电流、可重新配置为树形拓扑的近树时钟网络的综合

基本信息

批准号：
1755825
负责人：
Rickard Ewetz
金额：
$ 17.45万
依托单位：
The University of Central Florida Board of Trustees
依托单位国家：
美国
项目类别：
Standard Grant
财政年份：
2018
资助国家：
美国
起止时间：
2018-07-01 至 2022-06-30
项目状态：
已结题

来源：
https://www.nsf.gov/awardsearch/showAward?AWD_ID=1755825&HistoricalAwards=false
关键词：
CRII SHF Synthesis Near Tree

项目摘要

Many very large scale integration circuits deployed in the Internet of Things and in various high performance applications are required to support the use of high performance and low performance modes in order to minimize power consumption. Such circuits are synchronized by a clock signal that is distributed using a clock network. The clock network is required to reliably deliver the clock signal even while the circuit is under the influence of manufacturing and environmental variations. This research project will result in a clock network synthesis tool that is capable of reliably synchronizing components on circuits that operate in multiple modes. Moreover, a course on computer-aided design and research opportunities will be provided to students at the University of Central Florida. The robustness and power consumption of a clock network is mainly dependent on the topology of the network. Existing clock networks have a topology in the form of a tree, near-tree, or non-tree. In this project, a synthesis tool that is capable of constructing clock networks with a mode reconfigurable topology will be developed. In high performance modes, the required robustness to variations is provided by reconfiguring the clock network into a near-tree topology. In low-performance modes, the power consumption is reduced by reconfiguring the clock network into a tree topology. Moreover, the proposed clock network structure has no short circuit current, regardless of whether the topology is reconfigured to be in the form of a tree or near-tree. No short circuit current is introduced in the proposed structure because there is only a single gate driving each net of interconnects. In particular, the project involves developing an entire-clock-network-at-the-same-time methodology. Techniques of reconfiguring the topology and improving the robustness of delivering both the rising and falling edge of the clock signal will be explored.This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.

需要在物联网和各种高性能应用中部署的许多非常大的集成电路来支持高性能和低性能模式的使用，以最大程度地减少功耗。这样的电路通过使用时钟网络分布的时钟信号同步。即使电路受到制造和环境变化的影响，也需要时钟网络可靠地传递时钟信号。该研究项目将产生一种时钟网络合成工具，该工具能够在以多种模式下运行的电路上可靠地同步组件。此外，将向佛罗里达州中部大学的学生提供有关计算机辅助设计和研究机会的课程。时钟网络的稳健性和功耗主要取决于网络的拓扑。现有的时钟网络具有树，近树或非树的形式。在此项目中，将开发能够构建具有模式可重构拓扑的时钟网络的合成工具。在高性能模式下，通过将时钟网络重新配置为近树拓扑来提供对变化所需的鲁棒性。在低性能模式下，通过将时钟网络重新配置为树拓扑来降低功耗。此外，所提出的时钟网络结构没有短路电流，而不管拓扑是否以树或近树的形式重新配置为。提出的结构中没有任何短路电流引入，因为只有一个门驱动每个互连网。特别是，该项目涉及开发整个锁定网络的时间方法。将探索重新配置拓扑并提高交付时钟信号上升边缘和下降边缘的鲁棒性的技术。该奖项反映了NSF的法定任务，并被认为是通过基金会的智力优点和更广泛影响的评估标准来评估值得通过评估来支持的。

项目成果

期刊论文数量（15）

专著数量（0）

科研奖励数量（0）

会议论文数量（0）

专利数量（0）

Computational Restructuring: Rethinking Image Processing using Memristor Crossbar Arrays

DOI：
10.23919/date48585.2020.9116255
发表时间：
2020-03
期刊：
2020 Design, Automation & Test in Europe Conference & Exhibition (DATE)
影响因子：
0
作者：
Baogang Zhang;Necati Uysal;Rickard Ewetz
通讯作者：
Baogang Zhang;Necati Uysal;Rickard Ewetz

Accelerating AI Applications using Analog In-Memory Computing: Challenges and Opportunities

DOI：
10.1145/3453688.3461746
发表时间：
2021-06
期刊：
Proceedings of the 2021 on Great Lakes Symposium on VLSI
影响因子：
0
作者：
Shravya Channamadhavuni;Sven Thijssen;Sumit Kumar Jha;Rickard Ewetz
通讯作者：
Shravya Channamadhavuni;Sven Thijssen;Sumit Kumar Jha;Rickard Ewetz

Synthesis of Clock Networks with a Mode Reconfigurable Topology and No Short Circuit Current

具有模式可重构拓扑且无短路电流的时钟网络的综合

DOI：
10.1145/3372780.3375559
发表时间：
2020
期刊：
ISPD '20: Proceedings of the 2020 International Symposium on Physical Design
影响因子：
0
作者：
Uysal, Necati;Cabrera, Juan Ariel;Ewetz, Rickard
通讯作者：
Ewetz, Rickard

Fast Resilient-Aware Data Layout Organization for Resistive Computing Systems

DOI：
10.1109/isvlsi49217.2020.00023
发表时间：
2020-07
期刊：
2020 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)
影响因子：
0
作者：
Baogang Zhang;M. G. Sarwar Murshed;Faraz Hussain;Rickard Ewetz
通讯作者：
Baogang Zhang;M. G. Sarwar Murshed;Faraz Hussain;Rickard Ewetz

Representable Matrices: Enabling High Accuracy Analog Computation for Inference of DNNs using Memristors

DOI：
10.1109/asp-dac47756.2020.9045101
发表时间：
2019-11
期刊：
2020 25th Asia and South Pacific Design Automation Conference (ASP-DAC)
影响因子：
0
作者：
Baogang Zhang;Necati Uysal;Deliang Fan;Rickard Ewetz
通讯作者：
Baogang Zhang;Necati Uysal;Deliang Fan;Rickard Ewetz

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Rickard Ewetz其他文献

Cost-Effective Robustness in Clock Networks Using Near-Tree Structures

使用近树结构的时钟网络具有成本效益的鲁棒性

DOI：
10.1109/tcad.2015.2391253
发表时间：
2015
期刊：
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
影响因子：
2.9
作者：
Rickard Ewetz;Cheng
通讯作者：
Cheng