A Multi-Level Test Approach for Improving Reliability and Performance of Nanometer Technology Designs

提高纳米技术设计可靠性和性能的多级测试方法

• 批准号: 1565404
• 负责人: Mark Tehranipoor
• 金额: $ 8.02万
• 依托单位: University of Florida
• 依托单位国家: 美国
• 项目类别: Continuing Grant
• 财政年份: 2015
• 资助国家: 美国
• 起止时间: 2015-07-22 至 2017-05-31
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=1565404&HistoricalAwards=false
• 关键词: Multi; Level; Test; Approach; Improving

Circuit reliability, process variations, and environmental variations have become major challenges to address in advanced integrated circuit designs, especially for parts deployed in critical-life applications such as automotive, medical devices, aerospace, etc. The goal of this project is to develop novel and efficient test infrastructures, multi-level test approaches, and methods to eliminate wasteful guardband for improving performance and reliability of the circuit throughout its lifetime operation under any workload. The intellectual merits include (1) design of new test and measurement infrastructure while targeting aging, minimum available slack, noise, and timing uncertainties in the circuit, (2) generation of test patterns considering different noise/workload conditions on target paths and selection of paths to be targeted for test and reliability analysis, (3) analyzing the measurement data at three different levels, namely manufacturing test and silicon validation, system bring up, and in-the-field test, and finally (4) analyzing data collected from a SOC design fabricated in an advanced technology node. This project will lead to reduced design re-spin and shrinking gap between manufacturing test and system test, thereby lowering manufacturing cost. The results of this project will alleviate debugging and diagnosis problems. Resulting benefits for society include: (i) more reliable electronic systems for critical applications; (ii) cheaper and more dependable computing platforms; (iii) realization of the much sought-after goal of "zero defects" in the field for automotive, medical, and space applications. Students involved in this research will be prepared for the semiconductor industry workforce.

电路可靠性、工艺变化和环境变化已成为先进集成电路设计中需要解决的主要挑战，特别是对于汽车、医疗设备、航空航天等关键寿命应用中部署的部件。该项目的目标是开发新颖的高效的测试基础设施、多级测试方法以及消除浪费的保护带的方法，以提高电路在任何工作负载下的整个生命周期运行的性能和可靠性。其智力优点包括 (1) 设计新的测试和测量基础设施，同时针对电路中的老化、最小可用裕度、噪声和时序不确定性，(2) 生成测试模式，考虑目标路径上的不同噪声/工作负载条件并选择测试和可靠性分析的目标路径，(3) 分析三个不同级别的测量数据，即制造测试和硅验证、系统启动和现场测试，最后 (4) 分析从采用先进技术节点制造的 SOC 设计。该项目将减少设计重新设计并缩小制造测试和系统测试之间的差距，从而降低制造成本。该项目的结果将缓解调试和诊断问题。由此给社会带来的好处包括：(i) 关键应用的电子系统更加可靠； (ii) 更便宜、更可靠的计算平台； (iii) 实现汽车、医疗和航天应用领域备受追捧的“零缺陷”目标。参与这项研究的学生将为成为半导体行业的劳动力做好准备。