XPS: FULL: CCA: Collaborative Research: SPARTA: a Stream-based Processor And Run-Time Architecture

XPS：完整：CCA：协作研究：SPARTA：基于流的处理器和运行时架构

• 批准号: 1547036
• 负责人: Ahmed Louri
• 金额: $ 30.73万
• 依托单位: George Washington University
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 2015
• 资助国家: 美国
• 起止时间: 2015-05-15 至 2020-07-31
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=1547036&HistoricalAwards=false
• 关键词: XPS; FULL; CCA; Collaborative; Research

Computer systems have undergone a fundamental transformation recently, from single‐core processors to devices with increasingly higher core counts within a single chip. The semi‐conductor industry now faces the infamous power and utilization walls, that is, physical constraints such as levels of power and energy consumption, but also reliability of the various components, must be taken into account not only during the chip fabrication process, but also when generating machine code and during program execution. To meet these challenges, heterogeneity in design, both at the architecture and technology levels, will be the prevailing approach for energy efficient computing as specialized cores, accelerators, and graphical processing units (GPUs) can eliminate the energy overheads of general‐purpose homogeneous cores. However, with future technological challenges pointing in the direction of on‐chip heterogeneity, and because of the traditional difficulty of parallel programming, it becomes imperative to produce new system software stacks that can take advantage of the heterogeneous hardware. This project proposes to rethink the whole hardware‐software interface, by researching novel ways to design many‐core chip architectures and weaving heterogeneous components together and binding them by a fast and energy efficient on‐chip interconnection network. On top of it will lay a system software layer to efficiently drive applications and map them onto the best suited components of the chip. Both the hardware and software layer are encompassed by a novel execution model, which describes how to orchestrate the various parts of a program in the most efficient way (be it with respect to power and energy, performance, or reliability). To achieve these goals, the development of a new model of computation called SPARTA (Stream-based Processor And RunTime Architecture) is proposed. The proposed model combines a new runtime and compiler technology with a hierarchical heterogeneous many‐core chip and features hardware mechanisms for stream‐based fine‐grain program execution models to be reflected in different new software/hardware systems. Many issues are be envisioned, including programmability, scalability, performance evaluation, and power efficiency. Specifically, the goal is to identify the major challenges and obstacles toward an efficient exploitation of parallelism and scalability. To do so, traditional approaches will be re-evaluated by studying a collection of representative programs. A vertical design methodology is then proposed to effectively address the above challenges through the SPARTA approach and its implementation. In particular, the proposed cross-layer methodology consists of (a) a programming/execution model that will combine the Codelet model (leveraging our past research in dataflow models and extensions) with generalized streams: the Streaming Codelets, (b) an architecture model that will efficiently support the Streaming Codelets in heterogeneous hardware, and (c) a system software Stack that will be capable of effectively mapping Streaming Codelets to the proposed architecture. Finally, a qualitative and quantitative study of SPARTA will be performed via selected benchmarks and a consolidated methodology based on experimentation and analysis. The holistic cross-layer design methodology spanning the hardware/software stack and the reliability techniques developed from this research will significantly impact next generation multi‐core and System‐on‐Chip (SoC) architectures with improvements in energy efficiency, programmability, performance and robustness.

计算机系统最近经历了根本性的转变，从单核处理器到单芯片内核心数量越来越多的设备。半导体行业现在面临着臭名昭著的功率和利用壁垒，即不仅在芯片制造过程中必须考虑功率和能耗水平等物理限制，而且还必须考虑各种组件的可靠性，而且在生成机器代码和程序执行期间也是如此。为了应对这些挑战，架构和技术层面的异构设计将成为节能计算的主流方法，因为专用核心、加速器和图形处理单元 (GPU) 可以消除通用的能源开销同质核心。然而，随着未来的技术挑战指向片上异构的方向，并且由于并行编程的传统困难，生产能够利用异构硬件的新的系统软件堆栈变得势在必行。该项目建议重新思考整个硬件/软件接口，通过研究设计多核心芯片架构的新方法，将异构组件编织在一起，并通过快速、节能的片上互连网络将它们绑定在一起。在其之上将放置一个系统软件层，以有效地驱动应用程序并将它们映射到最适合的芯片组件上。硬件和软件层都包含在一种新颖的执行模型中，该模型描述了如何以最有效的方式编排程序的各个部分（无论是在功率和能源、性能还是可靠性方面）。为了实现这些目标，建议开发一种称为 SPARTA（基于流的处理器和运行时架构）的新计算模型。所提出的模型将新的运行时和编译器技术与分层异构多核芯片相结合，并具有基于流的细粒度程序执行模型的硬件机制，以反映在不同的新软件/硬件系统中。可以预见许多问题，包括可编程性、可扩展性、性能评估和功效。具体来说，目标是确定有效利用并行性和可扩展性的主要挑战和障碍。为此，将通过研究一系列代表性项目来重新评估传统方法。然后提出了一种垂直设计方法，通过 SPARTA 方法及其实施来有效解决上述挑战。特别是，所提出的跨层方法包括（a）一个编程/执行模型，它将 Codelet 模型（利用我们过去在数据流模型和扩展方面的研究）与广义流：Streaming Codelet 相结合，（b）一个架构模型它将有效地支持异构硬件中的 Streaming Codelet，以及 (c) 一个能够有效地将 Streaming Codelet 映射到所提议的架构的系统软件堆栈。最后，将通过选定的基准和基于实验和分析的综合方法对 SPARTA 进行定性和定量研究。涵盖硬件/软件堆栈的整体跨层设计方法以及根据本研究开发的可靠性技术将显着影响下一代多核和片上系统 (SoC) 架构，并提高能效、可编程性、性能和鲁棒性。