SHF: Small: On-Die Learning: A Pathway to Post-Deployment Robustness and Trustworthiness of Analog/RF ICs

SHF:小型:片上学习:实现模拟/射频 IC 部署后稳健性和可信度的途径

基本信息

  • 批准号:
    1527460
  • 负责人:
  • 金额:
    $ 35万
  • 依托单位:
  • 依托单位国家:
    美国
  • 项目类别:
    Standard Grant
  • 财政年份:
    2015
  • 资助国家:
    美国
  • 起止时间:
    2015-07-15 至 2019-06-30
  • 项目状态:
    已结题

项目摘要

Towards enabling reliable computing and promoting technology trustworthiness, this project seeks to facilitate cost-effective realization of robust and trusted integrated circuits (ICs), with particular emphasis in the analog/RF domain. While manufactured ICs are subjected to extensive scrutiny in order to weed out defective or suspicious parts prior to their deployment, a variety of reasons such as silicon aging and adverse operational or environmental conditions might cause the performances of a previously healthy analog/RF IC to fail its design specifications. Similarly, field-activated triggers of hidden capabilities might cause a previously trusted analog/RF IC to exhibit malicious functionality. With analog/RF ICs now prevalent in most electronic systems, due to the rapid growth of wireless communications, sensor applications, and the Internet of Things (IoT), equipping them with robustness and trustworthiness evaluation mechanisms becomes paramount to the applications wherein they are deployed. The proposed research is complemented by educational and outreach activities, including development of a new educational module, by providing opportunities for graduate and undergraduate research in interdisciplinary projects spanning Electrical Engineering, Computer Science and Applied Mathematics, as well as exposure of local community members to the topics of self-test, self-calibration, and post-deployment trust evaluation of analog/RF ICs through tutorials and seminars organized by the Texas Analog Center of Excellence (TxACE) at the University of Texas at Dallas. More specifically, this project seeks to enhance post-deployment robustness and trustworthiness of analog/RF ICs by integrating machine learning-based on-die monitoring and calibration capabilities. The key focus of this project is the cost-effective integration of on-die learning capabilities, which can be trained to (i) determine whether an analog/RF IC complies with its specifications, (ii) calibrate its performances, and/or (iii) detect the activation of potentially malicious circuitry, based on simple measurements from on-chip sensors. Through design, fabrication and characterization of two different analog/RF ICs, this project seeks to demonstrate that on-die intelligence can be integrated to provide post-deployment self-test, calibration and trust evaluation capabilities.
为了实现可靠的计算和促进技术的可信度,该项目旨在促进稳健和可信赖的综合电路(ICS)的成本效益实现,并特别强调了模拟/RF域。尽管制造的IC受到了广泛的审查,以便在部署之前淘汰有缺陷或可疑的部分,但诸如硅老化以及不良操作或环境条件等各种原因可能会导致以前健康的模拟/RF IC的表现使其设计规格失败。同样,隐藏功能的现场激活触发器可能会导致先前信任的模拟/RF IC表现出恶意功能。由于无线通信,传感器应用和物联网(IoT)的快速增长,现在在大多数电子系统中都普遍存在模拟/RF IC(IoT),因此为它们提供了稳健性和可信赖性评估机制,这对于将其部署的应用程序至关重要。 The proposed research is complemented by educational and outreach activities, including development of a new educational module, by providing opportunities for graduate and undergraduate research in interdisciplinary projects spanning Electrical Engineering, Computer Science and Applied Mathematics, as well as exposure of local community members to the topics of self-test, self-calibration, and post-deployment trust evaluation of analog/RF ICs through tutorials and seminars organized by the得克萨斯州卓越中心(TXACE)位于达拉斯分校的德克萨斯大学。更具体地说,该项目旨在通过整合基于机器学习的ON-DIE监视和校准功能来增强模拟/RF IC的稳健性和可信度。该项目的重点是在DIE学习能力上的成本效益整合,可以培训以(i)确定模拟/RF IC是否符合其规格,(ii)校准其性能,以及/(iii)检测基于chon-Chip传感器的简单测量的潜在恶意电路的激活。通过设计,制造和表征两种不同的模拟/RF IC,该项目试图证明可以集成在Die Intelligence,以提供后部署后的自我测试,校准和信任评估功能。

项目成果

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Yiorgos Makris其他文献

Yiorgos Makris的其他文献

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{{ truncateString('Yiorgos Makris', 18)}}的其他基金

CISE-ANR: SHF: Small: CHAMELEON: CompreHending And Mitigating Error in AnaLog ImplEmentations of On-Die Neural Networks
CISE-ANR:SHF:小:CHAMELEON:理解并减轻片上神经网络模拟实现中的错误
  • 批准号:
    2214934
  • 财政年份:
    2022
  • 资助金额:
    $ 35万
  • 项目类别:
    Standard Grant
SaTC: TTP: Medium: Hardware Intellectual Property Protection through Hybrid ASIC/TRAP Integrated Circuit Design
SaTC:TTP:中:通过混合 ASIC/TRAP 集成电路设计保护硬件知识产权
  • 批准号:
    2155208
  • 财政年份:
    2022
  • 资助金额:
    $ 35万
  • 项目类别:
    Standard Grant
Phase I IUCRC University of Texas at Dallas: Center for Hardware and Embedded System Security and Trust (CHEST)
第一阶段 IUCRC 德克萨斯大学达拉斯分校:硬件和嵌入式系统安全与信任中心 (CHEST)
  • 批准号:
    1916750
  • 财政年份:
    2019
  • 资助金额:
    $ 35万
  • 项目类别:
    Continuing Grant
Planning IUCRC University of Texas at Dallas: Center for Hardware and Embedded System Security and Trust (CHEST)
规划 IUCRC 德克萨斯大学达拉斯分校:硬件和嵌入式系统安全与信任中心 (CHEST)
  • 批准号:
    1747773
  • 财政年份:
    2018
  • 资助金额:
    $ 35万
  • 项目类别:
    Standard Grant
Student Travel Support for 2017 IEEE VLSI Test Symposium
2017 年 IEEE VLSI 测试研讨会学生旅行支持
  • 批准号:
    1735673
  • 财政年份:
    2017
  • 资助金额:
    $ 35万
  • 项目类别:
    Standard Grant
Student Travel Support for 2016 IEEE VLSI Test Symposium
2016 年 IEEE VLSI 测试研讨会学生旅行支持
  • 批准号:
    1639728
  • 财政年份:
    2016
  • 资助金额:
    $ 35万
  • 项目类别:
    Standard Grant
TWC: Medium: Hardware Trojans in Wireless Networks - Risks and Remedies
TWC:中:无线网络中的硬件木马 - 风险和补救措施
  • 批准号:
    1514050
  • 财政年份:
    2015
  • 资助金额:
    $ 35万
  • 项目类别:
    Standard Grant
TWC: Small: Collaborative: Toward Trusted Third-Party Microprocessor Cores: A Proof Carrying Code Approach
TWC:小型:协作:走向可信的第三方微处理器核心:携带代码的证明方法
  • 批准号:
    1318860
  • 财政年份:
    2013
  • 资助金额:
    $ 35万
  • 项目类别:
    Standard Grant
Cross-Layer Intelligent System-Based Adaptive Power Conditioning for Robust and Reliable Mixed-Signal Multi-Core SoCs
基于跨层智能系统的自适应功率调节,用于稳健可靠的混合信号多核 SoC
  • 批准号:
    1255754
  • 财政年份:
    2013
  • 资助金额:
    $ 35万
  • 项目类别:
    Continuing Grant
TC: Small: THWART: Trojan Hardware in Wireless ICs - Analysis and Remedies for Trust
TC:小:THWART:无线 IC 中的木马硬件 - 信任分析和补救措施
  • 批准号:
    1149465
  • 财政年份:
    2011
  • 资助金额:
    $ 35万
  • 项目类别:
    Standard Grant

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