SBIR Phase I: Graphene On-Chip Interconnects

SBIR 第一阶段：石墨烯片上互连

• 批准号: 1315042
• 负责人: Kevin Brenner
• 金额: $ 15万
• 依托单位: Harper Laboratories
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 2013
• 资助国家: 美国
• 起止时间: 2013-07-01 至 2014-06-30
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=1315042&HistoricalAwards=false
• 关键词: SBIR; Phase; Graphene; Chip; Interconnects

This Small Business Innovation Research Phase I project proposes to replace Cu on-chip interconnects with a graphene technology. Nanoscale Cu interconnects that make electrical connections to active devices, mainly transistors, are an essential component of nearly all semiconductor chips. In Complementary Metal Oxide Semiconductor (CMOS) Integrated Circuits (ICs), this Cu interconnect fabric is applied as a separate component to the transistors that are embedded in the Si wafer. As the dimensions of these transistors are continually scaled down to improve performance (a trend that major chip manufacturers agree will continue for the next few decades), the Cu interconnect fabric must also be scaled in parallel. Whereas transistors improve performance with scaling, the electrical resistance of Cu interconnects rapidly increases when scaled due to intrinsic properties of the metal. This brings an abundance of interconnect pain points to chip manufacturers, limiting their competitive edge for high-performance and low-power processors. This project develops graphene on-chip interconnects that can replace Cu and facilitate future IC scaling. The broader impact/commercial potential of this project is the enabling of a tremendously diverse portfolio of technologies including, but not limited to, mobile computing / smartphones, implantable biomedical devices, and hybrid engine controllers and semiconductor chips cross-pollinate well into broad commercial applications. Scaling the dimensions of transistors and interconnects has defined the success that microelectronics (and now nanoelectronics) have enjoyed for nearly half a century. Technologies that facilitate continued scaling and keeping pace with Moore's Law are a must for chip manufacturers to maintain a competitive edge. With scaling comes faster performance, expanded capabilities, and greater reliability to all of the diverse applications that are driven by such chip technology.

这个小型企业创新研究阶段项目建议用石墨烯技术取代芯片上的芯片互连。 纳米级Cu互连将电气连接到主动设备（主要是晶体管）是几乎所有半导体芯片的重要组成部分。 在互补的金属氧化物半导体（CMOS）集成电路（ICS）中，该Cu互连织物被用作嵌入在Si Wefer中的晶体管的单独组件。 随着这些晶体管的尺寸不断缩小以提高性能（主要芯片制造商同意的趋势将在接下来的几十年中继续），因此CU互连织物也必须并行缩放。尽管晶体管通过缩放提高性能，但由于金属的固有特性，CU互连的电阻迅速增加。 这给芯片制造商带来了大量的互连疼痛，从而限制了其竞争优势，以实现高性能和低功率处理器。 该项目开发了石墨烯对芯片互连，可以取代CU并促进未来的IC缩放。 该项目的更广泛的影响 /商业潜力是使多样化的技术组合启用，包括但不限于移动计算 /智能手机，可植入的生物医学设备，以及混合发动机控制器和半导体芯片，将其交叉胶结良好地固定在广泛的商业应用中。扩展晶体管和互连的尺寸已经定义了微电子学（现在是纳米电子学）在近半个世纪中所享有的成功。筹码制造商必须保持竞争优势的必要条件，这是促进持续扩展并与摩尔定律保持同步的技术。 随着缩放的速度，性能更快，功能扩展以及对所有由这种芯片技术驱动的不同应用程序的可靠性更高。