SHF: Small: Shared Memory Architectures and Microarchitectures for Heterogeneous General-Purpose Chips

SHF：小型：异构通用芯片的共享内存架构和微架构

• 批准号: 1216695
• 负责人: Daniel Sorin
• 金额: $ 30万
• 依托单位: Duke University
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 2012
• 资助国家: 美国
• 起止时间: 2012-08-01 至 2016-07-31
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=1216695&HistoricalAwards=false
• 关键词: SHF; Small; Shared; Memory; Architectures

The computing industry is currently producing and developing chips that include processor cores of different types. The move towards heterogeneous chips is due to two trends: the ability to squeeze more transistors on each chip and the improved power-efficiency of using specific cores for specific purposes. This research project extends the inter-core communication systems and precise specifications of homogeneous chips to heterogeneous chips. The benefits of extending homogeneous communication paradigms include improved performance and improved power-efficiency, and preliminary results show orders of magnitude improvements in both metrics. Society relies upon computers for ever more purposes, and qualitatively improving their performance and power-efficiency are critical to future computing platforms. Furthermore, by extending homogeneous specification methodologies, this research project facilitates chip testing and validation for heterogeneous chips, which is a significant fraction of industry effort in chip development, and eases the programming of these chips, which is among the biggest challenges in computing today. This research project consists of two technical thrusts. The first thrust is the development of memory systems for heterogeneous chips. Rather than treat a heterogeneous chip as two distinct systems that happen to share a chip, the goal is to closely integrate the heterogeneous cores in a systematic fashion that enables most communication between cores to be performed via on-chip caches rather than via off-chip memory. The second research thrust is to extend the notion of a computer architecture--an implementation-independent specification of a processor's behavior--from homogeneous systems to chip-wide heterogeneous systems. This research project involves the design and experimental evaluation of heterogeneous processor chips, and the bulk of the experimental work uses full-system simulation and experiments on purchased hardware. The contributions of this project will be heterogeneous processor chips that have significantly greater performance and power-efficiency, as well as implementation-independent architectures for heterogeneous chips. Society will be using heterogeneous processor chips in personal computers, in smartphones, and via cloud-provided services. Qualitatively improving these chips will enhance user computing experiences and enable new and exciting computing applications.

计算行业目前正在生产和开发包括不同类型的处理器内核的芯片。 异构芯片的发展归因于两个趋势：在每个芯片上压缩更多晶体管的能力以及将特定内核用于特定目的而提高的能效。 该研究项目将同构芯片的核心间通信系统和精确规范扩展到异构芯片。 扩展同构通信范例的好处包括提高性能和提高能效，初步结果显示这两个指标都有数量级的改进。 社会越来越依赖计算机来实现更多的目的，从质量上提高计算机的性能和能效对于未来的计算平台至关重要。 此外，通过扩展同质规范方法，该研究项目促进了异构芯片的芯片测试和验证，这是芯片开发行业工作的重要组成部分，并简化了这些芯片的编程，这是当今计算领域的最大挑战之一。 该研究项目由两个技术主旨组成。 第一个推动力是异构芯片存储系统的开发。 目标不是将异构芯片视为碰巧共享芯片的两个不同系统，而是以系统方式紧密集成异构核心，使核心之间的大多数通信能够通过片上缓存而不是通过片外执行记忆。 第二个研究重点是将计算机体系结构的概念（处理器行为的独立于实现的规范）从同构系统扩展到芯片范围的异构系统。 该研究项目涉及异构处理器芯片的设计和实验评估，大部分实验工作采用全系统仿真和在购买的硬件上进行实验。 该项目的贡献将是具有显着更高性能和功效的异构处理器芯片，以及异构芯片的独立于实现的架构。 社会将在个人电脑、智能手机以及通过云提供的服务中使用异构处理器芯片。 对这些芯片进行定性改进将增强用户的计算体验，并实现新的、令人兴奋的计算应用。