SHF: Small: Directoryless Shared Memory Using Execution Migration

SHF：小型：使用执行迁移的无目录共享内存

• 批准号: 1116372
• 负责人: Srini Devadas
• 金额: $ 40万
• 依托单位: Massachusetts Institute of Technology
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 2011
• 资助国家: 美国
• 起止时间: 2011-09-01 至 2015-08-31
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=1116372&HistoricalAwards=false
• 关键词: SHF; Small; Directoryless; Shared; Memory

The increase in processor clock frequencies from 1980-2003 has slowed down significantly in recent years. To improve computer performance computer architects are exploring parallel architectures including many-core architectures. In a many-core or multi-core architecture, processor cores with relatively low complexity are connected to memory and to each other via high-bandwidth on-chip interconnect. The most popular programming model for multi-cores is that of shared memory. In this memory model, programmers write different threads that can run on different processors all of which can share a single memory space. This means that the on-chip cache memory on the multi-core chip should behave like a large shared cache. Unfortunately, current schemes for cache coherence either suffer from lack of scalability or require large directories at each core significantly increasing chip area and power. A directoryless cache coherence scheme is being investigated in this project that relies on the mechanism of execution migration. In execution migration, a thread?s context or state moves to the processor in whose cache the data resides. An important advantage of an execution migration architecture is that only a one-way trip is required to access data, since the thread moves to access data. In conventional data migration architectures, a round-trip is required to access data ? a request is sent to the location where the data resides and then the data is sent to the requesting thread. Further, only one copy of data need be present on chip if execution migration is used, since threads can move. This means that cache coherence is trivially ensured. Moreover, the chip can store more distinct data, since data is not replicated and this reduces off-chip access rates. Finally, an execution migration architecture can exploit the plentiful on-chip bandwidth available to speed up thread migration, thereby reducing data access latency.There are challenges associated with this architecture corresponding to contention for shared data across multiple threads, and the energy required to move thread contexts. The first challenge is being met through judicious replication of data at the program source level or compiler level. In particular, limited read copies of data are created across multiple threads. Since these copies only exist in between two writes to the data, coherence is ensured as before without need for complex coherence logic. However, contention for shared data is significantly reduced. The second challenge of energy consumption is being met through migration of partial thread contexts ? if a stack machine is used as the processor core, energy consumption can be reduced by migrating a subset of the thread context corresponding to the top part of the stack instead of the entire stack.In this project, an Execution Migration Machine with over 100 cores is being designed, and being evaluated using cycle-accurate simulation, and critical elements of the machine are being built on a Field Programmable Gate Array (FPGA). This project has the potential to meet the scalability and programmability challenges that face shared memory multi-core architectures. The Execution Migration Machine design will shed insight into how best thread migration can be used to enhance multi-core performance, possibly in combination with data migration. If successful, the project will impact the design of future multi-core processors through intelligent use of program and data migration.

近年来，从1980 - 2003年开始的处理器时钟频率的增加显着放缓。为了改善计算机性能，计算机架构师正在探索包括多核体系结构在内的并行体系结构。 在多核或多核体系结构中，复杂性相对较低的处理器核通过芯片互连连接到内存，并通过高频带宽度相互连接。多核最受欢迎的编程模型是共享内存的编程模型。 在此内存模型中，程序员编写可以在不同的处理器上运行的不同线程，所有这些线程都可以共享一个单一的存储空间。 这意味着多核芯片上的片上缓存内存应该像大型共享缓存一样行为。不幸的是，当前用于缓存连贯性的方案要么缺乏可扩展性，要么在每个核心上需要大型目录，会显着增加芯片面积和功率。该项目中正在研究一个无目录的缓存相干方案，该计划依赖于执行迁移的机制。在执行迁移中，线程的上下文或状态移至数据缓存数据所在的处理器。 执行迁移体系结构的一个重要优点是，由于线程移动到访问数据，因此只需要单向旅行才能访问数据。 在传统的数据迁移体系结构中，访问数据需要往返？将请求发送到数据居住的位置，然后将数据发送到请求线程。此外，如果使用执行迁移，则在芯片上只需要一个数据副本，因为线程可以移动。 这意味着缓存连贯性是微不足道的。 此外，芯片可以存储更多不同的数据，因为数据未复制，这会降低芯片访问率。 最后，执行迁移体系结构可以利用可用于加速线程迁移的大量芯片带宽，从而减少数据访问延迟。与此体系结构相关的挑战与跨多个线程的共享数据相对应，以及移动所需的能量线程上下文。 第一个挑战是通过在程序源级别或编译器级别上明智地复制数据来应对。 特别是，有限的数据副本是在多个线程之间创建的。由于这些副本仅存在于两个写入数据之间，因此可以像以前一样确保连贯性，而无需复杂的相干逻辑。但是，共享数据的争论大大降低。 通过部分线程上下文的迁移，正在应对能源消耗的第二个挑战？如果将堆栈计算机用作处理器核心，则可以通过迁移与堆栈的顶部相对应的线程的子集而不是整个堆栈。正在设计并使用循环精确的模拟进行评估，并且正在在可编程门阵列（FPGA）上构建机器的关键元素。该项目有可能满足面临共享内存多核体系结构的可扩展性和可编程性挑战。 执行迁移机器设计将洞悉如何使用最佳线程迁移来增强多核性能，并可能与数据迁移结合使用。如果成功，该项目将通过智能使用程序和数据迁移来影响未来多核处理器的设计。