SHF: Small: Collaborative Research: Design for Manufacturability for 3D ICs with Through Silicon Vias

SHF：小型：协作研究：具有硅通孔的 3D IC 的可制造性设计

• 批准号: 1018750
• 负责人: David Pan
• 金额: $ 20万
• 依托单位: University of Texas at Austin
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 2010
• 资助国家: 美国
• 起止时间: 2010-09-01 至 2015-08-31
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=1018750&HistoricalAwards=false
• 关键词: SHF; Small; Collaborative; Research; Design

Through-Silicon-Via (TSV) provides the possibility of arranging heterogeneous components across multiple dies at a fine level of granularity in 3D ICs. This can result in significant decrease in the overall wire length, delay, power, and form factor. Primarily due to their large size compared with other layout objects, however, TSVs cause significant non-uniform density distribution in various layers. This density issue is expected to cause trouble during chemical mechanical polishing (CMP) and require TSV-aware solutions. In addition, the CTE (coefficient of thermal expansion) mismatch between TSV copper and silicon causes significant thermal mechanical stress to the devices nearby during TSV manufacturing and circuit operation. This in turn affects the timing and power characteristics of the devices. The mechanical reliability of the substrate and devices are also affected by TSVs. However, little is known on what design tool and methodology changes are required to improve the manufacturability of TSV-based 3D ICs. This project would investigate three key DFM/DFR areas specific to 3D IC integration, namely, TSV-induced stress effect and its impact to the overall circuit timing and power, TSV impact to CMP and lithography, and TSV-induced reliability. Successful completion of the project would help us to gain in-depth understanding of manufacturability and reliability issues with 3D ICs and TSV technology and develop effective physical design solutions to overcome these issues. The proposal calls for a very strong collaboration between the researchers from the manufacturability and reliability modeling, simulation, and validation area and the researchers from circuit and physical design area for 3D ICs.

硅通孔 (TSV) 提供了在 3D IC 中以精细粒度水平跨多个芯片排列异构组件的可能性。这可能会导致总线路长度、延迟、功率和外形尺寸显着减少。然而，主要由于与其他布局对象相比，TSV 的尺寸较大，导致各层中的密度分布明显不均匀。这种密度问题预计会在化学机械抛光 (CMP) 过程中造成麻烦，因此需要 TSV 感知解决方案。此外，TSV 铜和硅之间的 CTE（热膨胀系数）不匹配会在 TSV 制造和电路运行期间对附近的器件造成显着的热机械应力。这反过来又影响设备的时序和功率特性。基板和器件的机械可靠性也受到 TSV 的影响。然而，对于需要改变哪些设计工具和方法来提高基于 TSV 的 3D IC 的可制造性，人们知之甚少。该项目将研究 3D IC 集成的三个关键 DFM/DFR 领域，即 TSV 引起的应力效应及其对整体电路时序和功耗的影响、TSV 对 CMP 和光刻的影响以及 TSV 引起的可靠性。该项目的成功完成将有助于我们深入了解3D IC和TSV技术的可制造性和可靠性问题，并开发有效的物理设计解决方案来克服这些问题。该提案要求来自可制造性和可靠性建模、仿真和验证领域的研究人员与来自 3D IC 电路和物理设计领域的研究人员之间进行非常强有力的合作。