CAREER: A Synergistic CAD Framework for Nanometer Design and Process Integration
职业生涯:用于纳米设计和工艺集成的协同 CAD 框架
基本信息
- 批准号:0644316
- 负责人:
- 金额:$ 41.02万
- 依托单位:
- 依托单位国家:美国
- 项目类别:Continuing Grant
- 财政年份:2007
- 资助国家:美国
- 起止时间:2007-09-01 至 2015-08-31
- 项目状态:已结题
- 来源:
- 关键词:
项目摘要
Proposal ID: 0644316Title: CAREER: A Synergistic CAD Framework for Nanometer Design and ProcessIntegrationPI: David PanInstitution: UT AustinAbstract:After four decades of Moore's Law empowered by CMOS scaling, the semiconductor industry is facing unprecedented design and manufacturing challenges. The industry is stuck with the 193nm optical lithography as the dominant integrated circuit manufacturing process, which is likely to remain so for at least another 5 years, for 45nm, 32nm, and even 22nm technology nodes. A prominent feature of the deep sub-wavelength lithography is its proximity, layout-dependent effect. It is estimated that the lithography and design-related yield losses may contribute to 80% or more of the total yield loss in nanometer designs. However, it is not well captured in existing design flows, from modeling to optimization. This project will develop a synergistic computer aided design (CAD) framework that enables holistic design and process integration. It will resort to the root causes of yield losses by developing a set of design-oriented yet variation-aware manufacturing/yield models, as well as geometrical and electrical characterizations using predictive virtual silicon images. Thus it will help to eliminate significant amount of uncertainties for yield analysis and optimization. Meanwhile, guided by the modeling framework, novel CAD algorithms will be developed at various abstraction levels and architecture explorations will be performed for multi-objective design/manufacturing optimizations. The project will further investigate design and process integration issues for emerging technologies such as nanolithography and hybrid CMOS/post-CMOS processes.The integrated education component of the project will train a diverse body of students in this highly crosscutting and important area, where the intersection and co-evolution of circuit design, CAD and manufacturing create an excellent opportunity for exposing students to multiple engineering disciplines. Taken together in a holistic manner, this project aims at filling the critical gaps between design/CAD and manufacturing/process to further extend the scaling and economic benefits of the Moore's Law.
提案 ID:0644316 标题:职业:纳米设计和工艺集成的协同 CAD 框架 PI:David Pan 机构:UT Austin 摘要:在 CMOS 缩放的摩尔定律支持下四十年之后,半导体行业面临着前所未有的设计和制造挑战。业界一直坚持 193nm 光学光刻作为主要的集成电路制造工艺,对于 45nm、32nm 甚至 22nm 技术节点来说,这种情况可能至少再持续 5 年。深亚波长光刻的一个突出特点是其邻近性、布局相关效应。据估计,光刻和设计相关的良率损失可能占纳米设计中总良率损失的 80% 或更多。然而,从建模到优化的现有设计流程并没有很好地捕捉到这一点。该项目将开发一个协同计算机辅助设计(CAD)框架,实现整体设计和流程集成。 它将通过开发一套面向设计但具有变化感知能力的制造/良率模型以及使用预测虚拟硅图像的几何和电气特性来解决良率损失的根本原因。因此,它将有助于消除产量分析和优化的大量不确定性。同时,在建模框架的指导下,将在不同的抽象层次上开发新颖的CAD算法,并对多目标设计/制造优化进行架构探索。该项目将进一步研究纳米光刻和混合 CMOS/后 CMOS 工艺等新兴技术的设计和工艺集成问题。该项目的综合教育部分将在这个高度交叉和重要的领域培训多元化的学生,其中交叉点电路设计、CAD 和制造的共同发展为学生接触多个工程学科创造了绝佳的机会。总体而言,该项目旨在填补设计/CAD 和制造/工艺之间的关键差距,以进一步扩大摩尔定律的规模和经济效益。
项目成果
期刊论文数量(0)
专著数量(0)
科研奖励数量(0)
会议论文数量(0)
专利数量(0)
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David Pan其他文献
On the complexity and accuracy of motion estimation using Lie operators
关于使用Lie算子的运动估计的复杂性和准确性
- DOI:
10.1109/ssst.2004.1295611 - 发表时间:
2004 - 期刊:
- 影响因子:0
- 作者:
M. Nalasani;David Pan - 通讯作者:
David Pan
Fixed Drug Eruption of the Penis Secondary to Sulfamethoxazole-Trimethoprim
继发于磺胺甲恶唑-甲氧苄啶的阴茎固定药疹
- DOI:
- 发表时间:
2006 - 期刊:
- 影响因子:0
- 作者:
N. Lawrentschuk;David Pan;A. Troy - 通讯作者:
A. Troy
The end of world literature?
世界文学的终结?
- DOI:
10.31577/wls.2023.15.3.7 - 发表时间:
2023 - 期刊:
- 影响因子:0.2
- 作者:
David Pan - 通讯作者:
David Pan
FIB Overview
FIB概述
- DOI:
- 发表时间:
2019 - 期刊:
- 影响因子:0
- 作者:
Chris Y. Park;A. Avishai;David Pan;B. Lewis;Alex Buxbaum - 通讯作者:
Alex Buxbaum
Outcome from percutaneous nephrolithotomy in patients with spinal cord injury, using a single‐stage dilator for access
使用单级扩张器进入脊髓损伤患者的经皮肾镜取石术的结果
- DOI:
- 发表时间:
2005 - 期刊:
- 影响因子:4.5
- 作者:
N. Lawrentschuk;David Pan;R. Grills;J. Rogerson;D. Angus;D. Webb;D. Bolton - 通讯作者:
D. Bolton
David Pan的其他文献
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{{ truncateString('David Pan', 18)}}的其他基金
Collaborative Research: SaTC: CORE: Medium: Security and Robustness for Intermittent Computing Using Cross-Layer Post-CMOS Approaches
协作研究:SaTC:CORE:中:使用跨层后 CMOS 方法的间歇计算的安全性和鲁棒性
- 批准号:
2303116 - 财政年份:2023
- 资助金额:
$ 41.02万 - 项目类别:
Continuing Grant
SHF: Medium: Integrating Human and Machine Intelligence for Next Generation Interactive Analog IC Design
SHF:媒介:集成人类和机器智能以实现下一代交互式模拟 IC 设计
- 批准号:
1704758 - 财政年份:2017
- 资助金额:
$ 41.02万 - 项目类别:
Continuing Grant
SHF: Small: Design/Technology Co-Optimization and Exploration in Emerging Scaling
SHF:小型:新兴扩展中的设计/技术协同优化和探索
- 批准号:
1718570 - 财政年份:2017
- 资助金额:
$ 41.02万 - 项目类别:
Standard Grant
Collaborative Research: From High-level Synthesis to Layout: a Cross-layer Methodology for Large-scale Reliable IC Design
协作研究:从高级综合到布局:大规模可靠IC设计的跨层方法
- 批准号:
1255816 - 财政年份:2013
- 资助金额:
$ 41.02万 - 项目类别:
Continuing Grant
SHF: SMALL: GOALI: Design for Manufacturability in Extreme Scaling with Emerging Nanolithography
SHF:小型:GOALI:利用新兴纳米光刻技术实现极限缩放的可制造性设计
- 批准号:
1218906 - 财政年份:2012
- 资助金额:
$ 41.02万 - 项目类别:
Standard Grant
SHF: Small: Collaborative Research: Design for Manufacturability for 3D ICs with Through Silicon Vias
SHF:小型:协作研究:具有硅通孔的 3D IC 的可制造性设计
- 批准号:
1018750 - 财政年份:2010
- 资助金额:
$ 41.02万 - 项目类别:
Standard Grant
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