SHF: Small: Collaborative Research: Design for Manufacturability of 3D ICs with Through Silicon Vias

SHF：小型：协作研究：带硅通孔的 3D IC 的可制造性设计

• 批准号: 1018216
• 负责人: Sung Lim
• 金额: $ 20万
• 依托单位: Georgia Tech Research Corporation
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 2010
• 资助国家: 美国
• 起止时间: 2010-09-01 至 2014-08-31
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=1018216&HistoricalAwards=false
• 关键词: SHF; Small; Collaborative; Research; Design

Through-Silicon-Via (TSV) provides the possibility of arranging heterogeneous components across multiple dies at a fine level of granularity in 3D ICs. This can result in significant decrease in the overall wire length, delay, power, and form factor. Primarily due to their large size compared with other layout objects, however, TSVs cause significant non-uniform density distribution in various layers. This density issue is expected to cause trouble during chemical mechanical polishing (CMP) and require TSV-aware solutions. In addition, the CTE (coefficient of thermal expansion) mismatch between TSV copper and silicon causes significant thermal mechanical stress to the devices nearby during TSV manufacturing and circuit operation. This in turn affects the timing and power characteristics of the devices. The mechanical reliability of the substrate and devices are also affected by TSVs. However, little is known on what design tool and methodology changes are required to improve the manufacturability of TSV-based 3D ICs. This project would investigate three key DFM/DFR areas specific to 3D IC integration, namely, TSV-induced stress effect and its impact to the overall circuit timing and power, TSV impact to CMP and lithography, and TSV-induced reliability. Successful completion of the project would help us to gain in-depth understanding of manufacturability and reliability issues with 3D ICs and TSV technology and develop effective physical design solutions to overcome these issues. The proposal calls for a very strong collaboration between the researchers from the manufacturability and reliability modeling, simulation, and validation area and the researchers from circuit and physical design area for 3D ICs.

通过 - 硅病毒（TSV）提供了在3D IC中以粒度良好水平的多个模具跨多个模具上排列异质组件的可能性。这可能会导致总线长度，延迟，功率和外形显着减少。但是，主要是由于它们与其他布局对象相比，TSV在各个层中引起明显的不均匀密度分布。预计该密度问题将在化学机械抛光期间造成麻烦，并且需要TSV感知溶液。此外，TSV铜和硅之间的CTE（热膨胀系数）在TSV制造和电路运行期间，TSV铜和硅之间的不匹配会给附近的设备带来明显的热机械应力。反过来，这会影响设备的时机和功率特征。底物和设备的机械可靠性也受TSV的影响。但是，对于提高基于TSV的3D IC的可制造性，需要哪些设计工具和方法论更改。该项目将调查特定于3D IC集成的三个关键DFM/DFR领域，即TSV诱导的应力效应及其对整个电路时机和功率的影响，TSV对CMP和光刻的影响以及TSV诱导的可靠性。该项目的成功完成将有助于我们深入了解3D IC和TSV技术的生产性和可靠性问题，并开发有效的物理设计解决方案来克服这些问题。该提案要求研究人员从制造性和可靠性建模，仿真和验证领域与3D IC的电路和物理设计领域的研究人员之间进行非常强烈的合作。