SHF:Small:Device/Circuit Co-design of Negative Capacitance Transistors

SHF:Small：负电容晶体管的器件/电路协同设计

• 批准号: 1718671
• 负责人: Sung Lim
• 金额: $ 45万
• 依托单位: Georgia Tech Research Corporation
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 2017
• 资助国家: 美国
• 起止时间: 2017-09-01 至 2022-08-31
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=1718671&HistoricalAwards=false
• 关键词: SHF; Small; Device; Circuit; Co

When the supply voltage of a transistor drops, its power consumption reduces significantly but at the cost of delay increase. A scientific breakthrough found in 2008 named negative capacitance states that if a ferroelectric material is used for the gate of a transistor, its delay does not degrade even when the voltage reduces. This remarkable effect has a potential to offer very low power yet high performance electronic switches. Existing studies have demonstrated such benefits at individual transistor-level, but its impact on large-scale circuits and systems has not been well studied. The goal of the proposed research is to quantify these benefits first and then to develop ways to further the benefits. The project, by design, is interdisciplinary in nature and will cover a large range of topics from material science, device engineering to circuit design. The project is expected to provide a unique and interdisciplinary experience for the participating graduate and undergraduate students. The STEM outreach and education programs described will help high school and lower-level college students to seek further studies and careers in semiconductor science and engineering.The team proposes a holistic approach to negative capacitance transistor technology that incorporates experimental research at the most fundamental material-device level, going all the way up to the full chip level circuit simulations. They will develop physics-based compact models for their experimental devices and use these experimentally calibrated models to investigate the performance of negative capacitance transistors corresponding to advance technology nodes such as 10 nm and 7 nm. These models will serve as the intermediary that will translate the results from the basic experiments for chip-level simulations. Large-scale full-chip designs targeting internet-of-things to high-performance applications will be built and optimized to maintain the device superiority all the way up to system and circuit-level. For negative capacitance technology to successfully resolve the power dissipation bottleneck in computing and spur new paradigms in electronics, disjoint research in each individual levels in the hierarchy will not bring about the necessary breakthroughs. The team will develop an approach where all aspects of physics, materials, devices, compact models and circuits are optimized in a self-consistent manner.

当晶体管的供应电压下降时，其功耗会大大降低，但以延迟增加为代价。在2008年发现的一个科学突破命名为负电容，指出，如果将铁电材料用于晶体管的门，即使电压降低，它的延迟也不会降解。这种显着的效果有可能提供非常低的功率但高性能电子开关。现有的研究表明，在单个晶体管级别上有这种好处，但是它对大型电路和系统的影响尚未得到很好的研究。拟议的研究的目的是首先量化这些收益，然后开发进一步收益的方法。根据设计，该项目本质上是跨学科的，将涵盖从材料科学，设备工程到电路设计的各种主题。预计该项目将为参与的研究生和本科生提供独特的跨学科体验。 STEM宣传和教育计划所描述的将帮助高中和低级大学生寻求进一步的学习和职业在半导体科学和工程学方面。该团队提出了一种整体方法，以实现负电容晶体管技术，该方法将实验研究纳入最基本的材料设备水平，并一直延伸到整个CHIP Level Level Cource Mimulations。他们将为实验设备开发基于物理的紧凑型模型，并使用这些实验校准的模型来研究对应于高级技术节点（例如10 nm和7 nm）的负电容晶体管的性能。这些模型将用作中介机构，该中介将转换芯片级模拟的基本实验的结果。将建立和优化针对高性能应用程序的大型全芯片设计，以将设备的优势保持到系统和电路级别。为了使负电容技术成功地解决计算中的功率耗散瓶颈，并刺激了电子产品中的新范式，层次结构中每个单个级别的脱节研究都不会带来必要的突破。该团队将开发一种方法，以自动持续的方式优化物理，材料，设备，紧凑型模型和电路的各个方面。

项目成果

On the Microscopic Origin of Negative Capacitance in Ferroelectric Materials: A Toy Model

• DOI: 10.1109/iedm.2018.8614574
• 发表时间: 2018-12
• 期刊: 2018 IEEE International Electron Devices Meeting (IEDM)
• 作者: A. Khan

Cross-Domain Optimization of Ferroelectric Parameters for Negative Capacitance Transistors—Part I: Constant Supply Voltage

负电容晶体管铁电参数的跨域优化——第一部分：恒定电源电压

• DOI: 10.1109/ted.2019.2955018
• 发表时间: 2020
• 期刊: IEEE Transactions on Electron Devices
• 影响因子: 3.1
• 作者: Pentapati, Sai;Perumal, Rakesh;Khandelwal, Sourabh;Hoffmann, Michael;Lim, Sung Kyu;Khan, Asif I.
• 通讯作者: Khan, Asif I.

Full Chip Power Benefits with Negative Capacitance FETs

负电容 FET 带来全芯片功率优势

• 发表时间: 2017
• 期刊: Proceedings - International Symposium on Low Power Electronics and Design
• 作者: Samal, Sandeep;Khandelwal, Sourabh;Khan, Asif;Salahuddin, Sayeef;Hu, Chenming;Lim, Sung Kyu
• 通讯作者: Lim, Sung Kyu

Antiferroelectricity in lanthanum doped zirconia without metallic capping layers and post-deposition/-metallization anneals

• DOI: 10.1063/1.5037185
• 发表时间: 2018-05
• 期刊: Applied Physics Letters
• 影响因子: 4
• 作者: Z. Wang;Anthony A. Gaskell;M. Dopita;D. Kriegner;Nujhat Tasneem;Jerry Mack;N. Mukherjee;Z. Karim;A. Khan

Experimental Demonstration of Ferroelectric Spiking Neurons for Unsupervised Clustering

• DOI: 10.1109/iedm.2018.8614586
• 发表时间: 2018-12
• 期刊: 2018 IEEE International Electron Devices Meeting (IEDM)
• 作者: Z. Wang;Brian Crafton;Jorge Gomez;R. Xu;Aileen Luo;Z. Krivokapic;L. Martin;S. Datta;A. Raychowdhury;A. Khan