Collaborative Resarch: Targeting Multi-Core Clock Performance Gains in the Face of Extreme Process Variations

协作研究：在极端工艺变化的情况下瞄准多核时钟性能增益

基本信息

批准号：
0903454
负责人：
Abhijit Chatterjee
金额：
$ 18.12万
依托单位：
Georgia Tech Research Corporation
依托单位国家：
美国
项目类别：
Standard Grant
财政年份：
2009
资助国家：
美国
起止时间：
2009-09-15 至 2013-08-31
项目状态：
已结题

来源：
https://www.nsf.gov/awardsearch/showAward?AWD_ID=0903454&HistoricalAwards=false
关键词：
Collaborative Resarch Targeting Multi Core

项目摘要

The objective of this research is to overcome barriers limiting multicore processor clock frequencies and to achieve faster clock and data throughput rates with technology scaling than currently possible. The approach is to design hardware and software infrastructure into multicore processors that enables low cost comparison testing of the individual processor cores and test driven tuning of processor circuitry for high-speed core operation. The intellectual merit of this work lies in the ability of the underlying test and adaptation algorithms to extract the maximum amount of performance from the process cores that they are capable of delivering under inter and intra die process variations and electrical field degradation. Such adaptation is achieved with limited test and diagnosis cost while allowing possible "test escapes" to be handled in a fail-safe manner that does not result in a system crash. The diagnostics information generated is used to tune individual processor core circuitry for speed purposes. The broader impacts of this research include the ability to run advanced applications on multicore processors in, for example, future 4G mobile wireless systems including high definition video, interactive displays, image processing, data mining algorithms and other pervasive computing tasks that demand high processor throughput at low power for low heat dissipation and high device reliability. The project will also enable training of students and industry personnel in a new interdisciplinary field that involves fundamental concepts from electrical engineering, device physics and computer science through prototype demonstrations, seminars, workshops, cooperative research and student internships in industry.

这项研究的目的是克服限制多核心处理器时钟频率的障碍，并以技术缩放的速度实现更快的时钟和数据吞吐率。该方法是将硬件和软件基础架构设计到多层处理器中，该处理器可以对单个处理器内核进行低成本比较测试，并对高速核心操作的处理器电路进行测试驱动的调整。这项工作的智力优点在于基础测试和适应算法的能力，可以从工艺核心中提取最大的性能量，它们能够在跨间和内部的模具过程变化和电场降解下传递。通过有限的测试和诊断成本来实现这种适应性，同时允许以故障安全的方式处理可能的“测试逃逸”，而不会导致系统崩溃。生成的诊断信息用于调整单个处理器核心电路以进行速度。这项研究的更广泛的影响包括能够在例如未来的4G移动无线系统中运行高级处理器的高级应用程序，包括高清视频，交互式显示，图像处理，数据挖掘算法和其他普遍存在的计算任务，这些任务需要低功耗以低热量散热和高设备的可靠性，需要高处理器吞吐量。该项目还将在一个新的跨学科领域中培训学生和行业人员，该领域涉及电气工程，设备物理和计算机科学的基本概念，通过原型演示，研讨会，研讨会，讲习班，合作研究和行业的学生实习。