CAREER: Programming Interfaces and Hardware Designs for a Polymorphic Multicore Cache Architecture

职业：多态多核缓存架构的编程接口和硬件设计

• 批准号: 0845157
• 负责人: Thomas Wenisch
• 金额: $ 40万
• 依托单位: Regents of the University of Michigan - Ann Arbor
• 依托单位国家: 美国
• 项目类别: Continuing Grant
• 财政年份: 2009
• 资助国家: 美国
• 起止时间: 2009-02-15 至 2015-01-31
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=0845157&HistoricalAwards=false
• 关键词: CAREER; Programming; Interfaces; Hardware; Designs

The semiconductor industry has hit a wall - chip-level power and cooling constraints have slowed the march of clock frequency, forcing industry to instead bet on multicore to provide energy-efficient performance scalability. Although the multicore trend poses daunting challenges for application developers, it also creates new opportunities unavailable in traditional multi-chip multiprocessors: the drastic change in the relative costs of on-chip communication and computation enable application designs with tightly-coupled threads and frequent sharing that would prove latency- and bandwidth-prohibitive in traditional multiprocessors. Unfortunately, current multicore memory systems are inflexible and poorly-suited to support coordinated execution, as they provide no direct means for core-to-core communication or to optimize data placement on chip. Moreover, intra-chip access patterns vary drastically across applications - there is no one-size-fits-all static cache architecture. To address these deficiencies, this project seeks to develop a Polymorphic Multicore Cache Architecture (PMCA) - a modular on-chip cache design where software configures primitive hardware mechanisms to provide a cache architecture suited to a specific workload. The PMCA concept will be pursued along three fronts: First, PMCA?s architectural interface and behavioral design through a full system, cycle accurate simulation will be conducted. Second,language level constructs, software management policies, and virtualization of PMCA through FPGA based functional emulation will be investigated. Third, trade-offs in performance, area, and power for various designs will be examined.

半导体行业已经撞到了墙壁 - 芯片级功率和冷却​​限制减慢了时钟频率的行进，迫使工业倾向于押注多核心，以提供节能性能可扩展性。尽管多功能趋势对应用程序开发人员构成了艰巨的挑战，但它还在传统的多芯片多处理器中创造了不可用的新机会：片上通信和计算的相对成本的巨大变化使应用程序设计具有紧密耦合的线程和频繁的分享，并且可以证明延迟和带状延迟 - 在传统多型中。不幸的是，当前的多核心内存系统不灵活且适合支持协调的执行，因为它们没有提供核心与核心通信或优化芯片数据放置的直接手段。此外，芯片内访问模式在应用程序之间发生了巨大变化 - 没有一种适合所有静态缓存架构。为了解决这些缺陷，该项目旨在开发多态性的多形缓存体系结构（PMCA） - 一种模块化的片上缓存设计，软件配置原始硬件机制以提供适合特定工作负载的缓存架构。 PMCA概念将沿三个方面进行：首先，PMCA的建筑界面和行为设计通过完整的系统，将进行周期精确的模拟。其次，将研究通过基于FPGA的功能仿真对PMCA进行语言级别构建体，软件管理策略和虚拟化。第三，将检查各种设计的性能，区域和功率的权衡。