CPA-DA Collaborative Research: Research on Benchmarking and Robustness of VLSI Sizing Optimizations

CPA-DA 合作研究：VLSI 规模优化的基准测试和鲁棒性研究

• 批准号: 0811832
• 负责人: Puneet Gupta
• 金额: --
• 依托单位: University of California-Los Angeles
• 依托单位国家: 美国
• 项目类别: Continuing Grant
• 财政年份: 2008
• 资助国家: 美国
• 起止时间: 2008-08-01 至 2011-07-31
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=0811832&HistoricalAwards=false
• 关键词: CPA; DA; Collaborative; Research; Benchmarking

Proposal IDs: 0811832 & 0811866PI names: Andrew Kahng & Puneet GuptaTitle: Collaborative Research: Research on Benchmarking and Robustness of VLSI Sizing OptimizationsInst: UCSD & UCLAABSTRACTThe proposed research will investigate the ?sizing? optimizations that underlie all practical tradeoffs of integrated-circuit area, delay and power metrics. The intellectual merit of our proposed research stems from its broad and multi-pronged attack on a fundamental type of design optimization. The PIs will investigate core aspects of optimization including technology strategy based on fast estimation of achievable solution quality, benchmarking of optimization heuristics and strengthening of iterative optimization heuristics by use of stronger move ?operators?. The PIs will also address fundamental changes to the optimization context such as the potential need for statistical optimization in a regime of uncontrollable manufacturing variability and the need for incremental optimization under the regime of evolving process models.The broader impact of the proposed research lies in helping chip designers and manufacturers reduce design turnaround time in addition to IC area, delay and power metrics. This will enable the design of more complex and functional products within a given cost and power envelope; as such, our proposed research will have very substantial research and commercial impact. Other impacts will include open-source tools that will establish a baseline and foundation for further work by other research groups, preventing the wasted effort of reinventing the wheel that is endemic to experimental research today.

Proposal IDs: 0811832 & 0811866PI names: Andrew Kahng & Puneet GuptaTitle: Collaborative Research: Research on Benchmarking and Robustness of VLSI Sizing OptimizationsInst: UCSD & UCLAABSTRACTThe proposed research will investigate the ?sizing?综合电路区域，延迟和功率指标的所有实际权衡的优化。我们提出的研究的智力优点源于其对基本设计优化类型的广泛而多管齐的攻击。 PI将基于快速估算可实现的解决方案质量的快速估算，优化启发式方法的基准测试以及通过使用更强大的移动？运算符？ PI还将解决对优化环境的根本变化，例如在不可控制的制造可变性方面进行统计优化的潜在需求，以及在不断发展的过程模型的制度下进行增量优化的需求。拟议的研究的更广泛的影响在于帮助芯片设计人员和制造商减少设计周转时间，从而减少了IC领域的设计周转时间。这将使在给定的成本和功率信封内设计更复杂和功能的产品；因此，我们提出的研究将具有非常重大的研究和商业影响。其他影响还将包括开源工具，该工具将为其他研究小组的进一步工作建立基准和基础，从而阻止了重塑当今实验研究的特有方案的浪费。