CSR--EHS: Collaborative Research: Hybrid Timing Analysis via Multi-Mode Execution

CSR--EHS：协作研究：通过多模式执行进行混合时序分析

• 批准号: 0720496
• 负责人: Frank Mueller
• 金额: $ 14万
• 依托单位: North Carolina State University
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 2007
• 资助国家: 美国
• 起止时间: 2007-08-01 至 2011-07-31
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=0720496&HistoricalAwards=false
• 关键词: CSR; EHS; Collaborative; Research; Hybrid

Current software design for safety-critical embedded systems requires stringent compliance with coding standards to ensure safety and reliability. A key additional requirement for real-time embedded systems is predictable timing behavior of software components, which requires that bounds on the worst-case execution time (WCET) of embedded software be determined. While static timing analysis yields verifiable bounds on the WCET, it cannot keep pace with architectural innovations and hardware performance variation due to chip fabrication scaling. This work contributes a fundamentally new approach to bounding the WCET with three major contributions: (1) Instead of simulating execution, actual execution in hardware is promoted to assess the WCET of a task. This approach not only renders tedious hardware modeling unnecessary but also confirms correct behavior regardless of architectural complexity or hardware variation. (2) The approach and its complexity are evaluated by FPGA synthesis. This assesses the feasibility of the design and validates a prototype implementation. (3) The impact of advanced architectural features is studied in a co-design space exploration, aimed to provide predictability and tight WCET bounds. The research conducted in this project advances existing science and technology through novel techniques in hardware and software design for safety-critical embedded real-time systems by providing high-confidence bounds on execution times; enhancing hardware architectures with support to assess execution times; and customizing hardware features via co-design to improve predictability. These capabilities directly benefit safety and reliability of software controlling, for example, aircraft and components of cars, thereby aiding the high-confidence design of embedded systems.

当前安全关键型嵌入式系统的软件设计需要严格遵守编码标准，以确保安全性和可靠性。实时嵌入式系统的一个关键附加要求是软件组件的可预测时序行为，这需要确定嵌入式软件的最坏情况执行时间 (WCET) 的界限。虽然静态时序分析在 WCET 上产生了可验证的界限，但由于芯片制造规模的扩大，它无法跟上架构创新和硬件性能变化的步伐。这项工作提供了一种从根本上限制 WCET 的新方法，具有以下三个主要贡献：（1）不是模拟执行，而是促进硬件中的实际执行来评估任务的 WCET。这种方法不仅不需要繁琐的硬件建模，而且无论架构复杂性或硬件变化如何，都可以确认正确的行为。 (2)通过FPGA综合评估了该方法及其复杂度。 这评估了设计的可行性并验证了原型的实现。 (3) 在协同设计空间探索中研究了先进建筑特征的影响，旨在提供可预测性和严格的 WCET 界限。 该项目中进行的研究通过为安全关键型嵌入式实时系统提供高置信度的执行时间界限，通过硬件和软件设计的新技术来推进现有的科学和技术；通过支持评估执行时间来增强硬件架构；通过协同设计定制硬件功能以提高可预测性。 这些功能直接有利于软件控制（例如飞机和汽车部件）的安全性和可靠性，从而有助于嵌入式系统的高可信度设计。