Error Correction Systems for Nano-Scale Fault-Tolerant Memories

纳米级容错存储器的纠错系统

• 批准号: 0634969
• 负责人: Bane Vasic
• 金额: $ 30万
• 依托单位: University of Arizona
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 2006
• 资助国家: 美国
• 起止时间: 2006-10-01 至 2010-09-30
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=0634969&HistoricalAwards=false
• 关键词: Error; Correction; Systems; Nano; Scale

In the proposed research, highly reliable memories made of unreliable components will be developedand characterized in terms of their complexity and ability to retain the stored information. The main challenge is that in nano-scale systems both the storage elements and logic gates are faulty. It is in contrast to the state-ofthe- art systems where only the memory elements are considered unreliable while error correction encoders and decoders are assumed to be made of reliable logic gates.The set of problems that will be addressed in this research can be condensed into the following question:given n memory cells and m universal logic gates which fail following a known random mechanism, what is the optimal memory architecture which stores the maximum number of information bits for the longest period of time with arbitrary low probability of error? This complex problem can be divided and reformulated in many ways, but, interestingly, even some of the most fundamental questions related to this problem are still unanswered. The most important question is related to the following two fundamentally different approaches in fault-tolerant memories: (i) To improve reliability, the logic gate resources may be invested into a von Neumann multiplexing scheme. In this way, one can build highly redundant reliable networks that simulate the function of universal logic gates, and then use such better gates to build an error correction encoder and decoder. (ii)Alternatively, the logic gate resources may be invested into building a more powerful error correcting code (i.e.,decoder) capable of handling both memory elements as well as logic gates errors. Which of these twoapproaches is optimal for a given failure mechanism? On a broad scale, is it better to deal with a reliability issue on a device or on a system level?Intellectual Merit:The unique feature of the nano-systems that both the storage elements and logic gates are unreliable makes the problem of ensuring fault-tolerance theoretically very important, because the process of error correction is not error-free as assumed in classical information theory. Making error correcting codes stronger and transmitters and receivers more complex will not necessarily improve the performance of a system. It is likely that for a given failure mechanism, there is a trade off between receiver complexity and its performance.Our approach to developing fault-tolerant memory architectures is based on a method developed byTaylor and refined by Kuznetsov. Taylor and Kuznetsov (TK) showed that memory systems have nonzerocomputational (storage) capacity, i.e. the redundancy necessary to ensure reliability grows asymptoticallylinearly with the memory size. Two fundamental open problems that will be addressed in this research aredetermining storage capacity of nano-scale memories and the development of capacity approaching fault-tolerant architectures. The equivalence of the restoration phase in the TK method and faulty Gallager-B algorithm (as explained in Project Description), will enable us to tackle these and other important problems in reliable storage on unreliable media using the large body of knowledge in codes on graphs and iterative decoding gained in the past decade.Broader Impact:This program will contribute significantly to the evolution of data storage technologies and the informationinfrastructure in the United States of America and abroad. Another important aspect is the establishment of atight interdisciplinary integration of knowledge in coding and signal processing, and nano-scale devices andsubsystems into programs benefiting undergraduate and graduate students at the University of Arizona and theindustrial technical research community.

在拟议的研究中，将开发由不可靠组件制成的高度可靠的记忆，并以其复杂性和保留存储信息的能力为特征。主要的挑战是，在纳米级系统中，存储元素和逻辑门都是错误的。它与最先进的系统形成鲜明对比，在该系统中，只有记忆要素被认为不可靠而误差校正编码器和解码器被假定由可靠的逻辑门制成。本研究中将解决的一系列问题可以凝结到以下问题中：给定n个记忆细胞和M的通用逻辑，该逻辑的最高效率是最高的，该逻辑的最高机制是最高的，该机构的最高机构是在最大的过程中，该信息的最高机构是be的最高机制，该机构的最大程度是be，该机构的最高范围是be的最高记忆，该信息的数字是be的最高范围。任意低错误概率？这个复杂的问题可以通过多种方式进行划分和重新制定，但是有趣的是，即使是与此问题有关的一些最根本的问题，仍然没有得到答复。最重要的问题是与以下两种易于故障的记忆的根本不同的方法有关：（i）为了提高可靠性，逻辑门资源可以投入到von Neumann多路复用方案中。这样，就可以构建高度冗余的可靠网络来模拟通用逻辑门的功能，然后使用这样的更好的门来构建错误校正编码器和解码器。 （ii）或者，可以将逻辑门资源投资用于构建更强大的错误校正代码（即解码器），能够处理两个内存元素以及逻辑门错误。对于给定的失败机制，这两种操作中的哪一个是最佳选择的？从广义上讲，在设备或系统级别上处理可靠性问题是否更好？智力优点：纳米系统的独特功能，存储元素和逻辑门都不可靠的问题使理论上非常重要，因为在经典信息信息理论中，误差纠正的过程并不是假定的。使错误纠正更强的校正代码更强大，发射器和接收器更复杂，不一定会改善系统的性能。对于给定的故障机制，接收器的复杂性与其性能之间存在权衡。我们开发容忍缺陷的内存体系结构的方法基于Bytaylor开发的方法，并由Kuznetsov进行了完善。泰勒（Taylor）和库兹尼托夫（Kuznetsov）（TK）表明，内存系统具有非二元（存储）容量，即确保可靠性随着记忆尺寸渐近地增长所需的冗余。这项研究将解决纳米级记忆的存储能力以及接近容忍断层耐受性耐受性的能力的两个基本开放问题。 TK方法中恢复阶段的等效性和错误的Gallager-B算法（如项目描述中所述），将使我们能够在不可靠的媒体上使用图形上的大量知识来解决这些和其他重要的问题，并在过去十次中获得的图形和迭代解码的大量知识将在过去的十二范围内获得贡献。美国和国外。另一个重要方面是建立Atight跨学科在编码和信号处理中的知识的整合，以及纳米级的设备和订阅系统，以使亚利桑那大学和工业技术研究社区的本科生和研究生受益。