VIrtual TEst STructure (VITEST)

虚拟测试结构（VITEST）

• 批准号: 0541297
• 负责人: Wojciech Maly
• 金额: $ 27.5万
• 依托单位: Carnegie-Mellon University
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 2006
• 资助国家: 美国
• 起止时间: 2006-08-15 至 2011-07-31
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=0541297&HistoricalAwards=false
• 关键词: VIrtual; TEst; STructure; VITEST

Prop ID: CCF-0541297 PI: Maly, Wojciech Institution: Carnegie-Mellon University Title: VIrtual TEst STructure (VITEST) AbstractModern Integrated Circuits (ICs) are built of elements so small that some of them may be too small to be fabricated correctly on everyone fabricated device. Art of modern IC manufacturing is in choosing such scale of miniaturization IC elements (typically transistors) that pushes available technology to its limits, i,e, to the stage in which number of fabricated ICs that work correctly is acceptable and at the same time the number of elements in a single IC as large as possible (by making them as small as possible).To achieve such a balance one must understand specific circumstances causing IC malfunction. Typically such knowledge is acquired by using special purpose test structures, which are fabricated instead of normal IC and therefore are wasting very expensive manufacturing capacity. The key idea of the research covered by this project is in the use of IC products themselves for calibration of manufacturing yield models. These models form a foundation of methodologies used for assessment probability of IC malfunctions.

提案 ID：CCF-0541297 PI：Maly，Wojciech 机构：卡内基梅隆大学 标题：虚拟测试结构 (VITEST) 摘要现代集成电路 (IC) 是由非常小的元件构建的，以至于其中一些可能太小而无法正确制造每个人都制造了设备。现代 IC 制造的艺术在于选择如此规模的小型化 IC 元件（通常是晶体管），从而将现有技术推向极限，即达到可以正确工作的制造 IC 数量可接受的阶段，同时单个 IC 中的元件数量尽可能多（通过使它们尽可能小）。为了实现这种平衡，必须了解导致 IC 故障的具体情况。通常，此类知识是通过使用专用测试结构来获得的，这些测试结构是代替普通 IC 制造的，因此浪费了非常昂贵的制造能力。该项目所涵盖的研究的关键思想是利用 IC 产品本身来校准制造良率模型。这些模型构成了用于评估 IC 故障概率的方法的基础。