NER: Exploring Nanodevices for Probabilistic Computing Architectures

NER：探索概率计算架构的纳米设备

• 批准号: 0403958
• 负责人: Alexander Zaslavsky
• 金额: $ 10万
• 依托单位: Brown University
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 2004
• 资助国家: 美国
• 起止时间: 2004-07-01 至 2006-06-30
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=0403958&HistoricalAwards=false
• 关键词: NER; Exploring; Nanodevices; Probabilistic; Computing

PROPOSAL NO: 0403958INSTITUTION: Brown UniversityPRINCIPAL INVESTIGATOR: Zaslavsky , AlexanderTITLE: NER: Exploring Nanodevices for Probabilistic Computing ArchitecturesAbstract:The progress of modern transistor-based digital technology has depended on shrinking silicon transistor to ever smaller sizes and integrating more of these transistors into logic circuits. At some point in the next decade, however, transistors will reach their ultimate physical size and circuits will contain so many transistors that some nonworking devices are inevitable. As a result, we may need both new types of devices to replace silicon transistors or new types of logic architectures that can tolerate some number of defective devices in a circuit, or both.The proposed exploratory research targets both of these issues. We propose to map our previously developed probabilistic computer architectures onto real experimental devices, that will be fabricated from carbon nanotube material. Conversely, the nonlinear characteristics of the nanotube device prototypes will provide the experimental inputs to designing more advanced fault-tolerant logic circuits.

提案号：0403958机构：布朗大学首席研究员：扎斯拉夫斯基，亚历山大标题：NER：探索概率计算架构的纳米器件摘要：现代基于晶体管的数字技术的进步依赖于将硅晶体管缩小到更小的尺寸并将更多的晶体管集成到逻辑电路中。 然而，在未来十年的某个时刻，晶体管将达到其最终的物理尺寸，电路将包含如此多的晶体管，以至于不可避免地会出现一些无法工作的设备。 因此，我们可能需要新型器件来取代硅晶体管，或者需要能够容忍电路中一定数量有缺陷器件的新型逻辑架构，或者两者兼而有之。所提出的探索性研究针对这两个问题。 我们建议将我们之前开发的概率计算机架构映射到由碳纳米管材料制造的真实实验设备上。 相反，纳米管器件原型的非线性特性将为设计更先进的容错逻辑电路提供实验输入。