Noise Simulation in Nanoscale Semiconductor Devices

纳米级半导体器件中的噪声仿真

• 批准号: 0306343
• 负责人: Giorgio Casinovi
• 金额: $ 20万
• 依托单位: Georgia Tech Research Corporation
• 依托单位国家: 美国
• 项目类别: Continuing Grant
• 财政年份: 2003
• 资助国家: 美国
• 起止时间: 2003-07-15 至 2006-06-30
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=0306343&HistoricalAwards=false
• 关键词: Noise; Simulation; Nanoscale; Semiconductor; Devices

The growth in the market for wireless communications devices has reached dramatic proportions in the past decade. This development has spurred rapid advances in RF integrated circuits technology. Competing requirements on the performance of RF circuits pose significant technical challenges at all levels, from architectural design to integrated circuit fabrication. In order to meet these challenges, significant advances in related computer-aided design (CAD) technology are also needed. The availability of innovative CAD tools that cover the entire design process is critical to the successful design of leading-edge RF systems. An important limiting factor affecting the performance of RF components is electrical noise, a phenomenon intrinsic to all electronic devices. The mechanisms responsible for the generation of electrical noise inside semiconductor transistors are poorly understood, and even less so in the case of devices whose size is in the nanoscale range. For this reason, currently it is very difficult, if not impossible, to assess the impact of noise on the performance of circuits built using nanoscale technology. The goal of this research project is the development of computer-aided software to simulate the mechanisms responsible for the generation of electrical noise in nanoscale semiconductor devices. The simulations will be used to develop improved and more accurate mathematical models of those mechanisms, which will be validated against data from experimental measurements available in the literature. These models will make it possible to realize aggressive designs of nanotechnology-based RF systems. Commercial use of the scientific results of this project will be facilitated by the Interconnect Focus Center, a research center established by the Semiconductor Industry Association at Georgia Tech, whose goal is to sustain the technology growth of the semiconductor industry by placing an emphasis on significant long-term research. Integration of research and education will be pursued through graduate and undergraduate courses and seminars and through the Georgia Tech Regional Engineering Program, a distance-learning program established in collaboration with other Georgia universities to offer innovative engineering education and to serve as catalyst for economic development.

在过去的十年中，无线通信设备市场的增长达到了惊人的程度。这一发展刺激了射频集成电路技术的快速进步。对射频电路性能的竞争要求在从架构设计到集成电路制造的各个层面都提出了重大的技术挑战。为了应对这些挑战，还需要相关计算机辅助设计（CAD）技术的重大进步。覆盖整个设计流程的创新 CAD 工具的可用性对于领先射频系统的成功设计至关重要。 影响射频元件性能的一个重要限制因素是电噪声，这是所有电子设备固有的现象。人们对半导体晶体管内部产生电噪声的机制知之甚少，对于尺寸在纳米级范围内的器件来说更是如此。因此，目前评估噪声对使用纳米级技术构建的电路性能的影响即使不是不可能，也是非常困难的。该研究项目的目标是开发计算机辅助软件来模拟纳米级半导体器件中产生电噪声的机制。这些模拟将用于开发这些机制的改进且更准确的数学模型，该模型将根据文献中提供的实验测量数据进行验证。这些模型将使实现基于纳米技术的射频系统的积极设计成为可能。 互连焦点中心将促进该项目科学成果的商业利用，该中心是由半导体行业协会在佐治亚理工学院建立的一个研究中心，其目标是通过重点关注长期的重要研究来维持半导体行业的技术增长。长期研究。研究和教育的整合将通过研究生和本科生课程和研讨会以及佐治亚理工学院区域工程项目来实现，该项目是与佐治亚州其他大学合作建立的远程学习项目，旨在提供创新的工程教育并成为经济发展的催化剂。