CAREER: Purdue Memory Access Based Caching Schemes

职业：基于普渡内存访问的缓存方案

• 批准号: 9875960
• 负责人: T Vijaykumar
• 金额: $ 20.5万
• 依托单位: Purdue Research Foundation
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 1999
• 资助国家: 美国
• 起止时间: 1999-03-01 至 2004-02-29
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=9875960&HistoricalAwards=false
• 关键词: CAREER; Purdue; Memory; Access; Based

CCR-9875960VijaykumarTraditionally, the gap between processor and main memory speeds has been bridged by placing a hierarchy of cache memories containing successive levels of slower, larger caches between the processor and main memory accesses that miss in the faster levels of the hierarchy underscoring the need for better cache hierarchy management.The ever-increasing number of on-chip transistors can be employed to track dynamic information relevant to memory accesses. This project investigates novel hardware techniques to allow flexible cache management without excessive overheads. The techniques comprise of (1) providing flexible management through high cache associativity, (2) providing a shortcut from instructions to cache frames to avoid the overhead of high associativity, (3) tracking the instructions that compute the address of a cache miss to initiate a prefetch by executing such address computations, early, and (4) tracking the instructions that access cache blocks to enable replacement of less useful blocks by more useful data. Performance achieved by the proposed hardware-based techniques is evaluated by testing widely used benchmarks through a detailed software simulator.

CCR-9875960VijaykumarTraditionally, the gap between processor and main memory speeds has been bridged by placing a hierarchy of cache memories containing successive levels of slower, larger caches between the processor and main memory accesses that miss in the faster levels of the hierarchy underscoring the need for better cache hierarchy management.The ever-increasing number of on-chip transistors can be用于跟踪与内存访问相关的动态信息。 该项目研究了新型的硬件技术，以允许灵活的高速缓存管理而没有过多的开销。 该技术包括（1）通过高缓存关联提供灵活的管理，（2）提供从指令到缓存框架的快捷方式，以避免高度关联性的开销，（3）跟踪指示的指示，以跟踪缓存的地址，以启动较少的指示来启动此类cache的启动范围，从而启动此类地址的有用的指示，并在执行此类地址的范围内，（4） 数据。 通过详细的软件模拟器测试广泛使用的基准测试，可以评估所提出的基于硬件技术的性能。