Presidential Faculty Fellows/Presidential Early Career Awards for Scientists and Engineers (PFF/PECASE): Power Estimation and Optimization in IC Design

总统教职研究员/总统科学家和工程师早期职业奖 (PFF/PECASE)：IC 设计中的功耗估计和优化

• 批准号: 9628999
• 负责人: Massoud Pedram
• 金额: $ 20万
• 依托单位: University of Southern California
• 依托单位国家: 美国
• 项目类别: Continuing Grant
• 财政年份: 1997
• 资助国家: 美国
• 起止时间: 1997-07-15 至 2000-09-30
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=9628999&HistoricalAwards=false
• 关键词: Presidential; Faculty; Fellows; Early; Career

This is developing a methodology and efficient techniques for evaluating and/or predicting power dissipation of CMOS circuits. The major components of the proposed methodology are survey sampling techniques, automata-based sequence compaction techniques, a behavioral/logic level co-simulation engine, regression-based power macro-modeling techliques, and information-theoretic models of power dissipation. Special emphasis is being given to parasitic capacitance estimation, input data modeling, impact of memory hierarchy and circuit architecture, and effects of nonlinear delay equations and custom wire load models on accuracy/efficiency trade-offs of the estimators. Concurrently, CAD methodologies and techniques for minimizing the power dissipation in VLSI circuits and systems are being developed. These are: low power optimization techniques and prototype software programs for system-level partitioning and hardware/software codesign, communication synthesis, multiple supply voltage scheduling, activity-driven register allocation and binding, bus encoding, state assignment for interacting finite state machines, logic restructuring and simplification, timing-driven placement, routing and zero-skew clock tree construction. Finally, power management techniques such as (serial or parallel) gated clocks, stoppable clocks, and dynamic switching between power modes are being studied and automated.

该项目正在开发一种用于评估和/或预测 CMOS 电路功耗的方法和有效技术。所提出方法的主要组成部分是调查采样技术、基于自动机的序列压缩技术、行为/逻辑级协同仿真引擎、基于回归的功率宏观建模技术以及功耗的信息理论模型。 特别强调寄生电容估计、输入数据建模、存储器层次结构和电路架构的影响，以及非线性延迟方程和定制线负载模型对估计器精度/效率权衡的影响。同时，正在开发用于最小化 VLSI 电路和系统中功耗的 CAD 方法和技术。这些是：用于系统级分区和硬件/软件协同设计的低功耗优化技术和原型软件程序、通信综合、多电源电压调度、活动驱动的寄存器分配和绑定、总线编码、用于交互有限状态机的状态分配、逻辑重组和简化、时序驱动的布局、布线和零偏斜时钟树构建。最后，诸如（串行或并行）门控时钟、可停止时钟和电源模式之间的动态切换等电源管理技术正在研究和自动化。