SHF: Small: A Cross-Layer Modeling and Optimization Framework Targeting FinFET-based Designs Operating in Multiple Voltage Regimes

SHF：小型：跨层建模和优化框架，针对在多个电压范围内运行的基于 FinFET 的设计

• 批准号: 1423680
• 负责人: Massoud Pedram
• 金额: $ 43万
• 依托单位: University of Southern California
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 2014
• 资助国家: 美国
• 起止时间: 2014-09-01 至 2018-02-28
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=1423680&HistoricalAwards=false
• 关键词: SHF; Small; Cross; Layer; Modeling

Recent studies emphasize the importance of energy-efficient computing for sustaining advancements in information technology and addressing critical societal challenges. The exploration of holistic power optimization and management solutions that cut across multiple layers of the computing stack and infrastructure to be studied in this project will better enable available opportunities for maximizing energy efficiency. The research will advance the state-of-the art in sub-10nm device design, modeling, and optimization, standard cell library design and characterization, circuit speed vs. energy efficiency vs. reliability trade space exploration, and heterogeneity modeling at the chip level. The challenges and opportunities in this research will provide directions for developing many of the technologies and approaches that are needed to design energy-efficient computing systems of the future and ensure sustainability of the information technology ecosystem. Education, outreach, and training programs enhanced by this project will include development of new educational modules, recruitment of minority and under-represented students, as well as undergraduate learning and research internship opportunities for undergraduates.From a technical standpoint, this project will innovate at two cross-layer boundaries: (i) Technology and Circuits, and (ii) Circuits and Architectures. More precisely, a first thrust of the research will focus on developing deeply-scaled (multi-gate) CMOS devices and logic cell libraries that offer high energy efficiency, fast switching speed, and reliability. A second thrust targets the design of low dynamic and standby power circuits, circuit designs capable of robust and energy-delay optimal operation in multiple voltage regimes, and means for effective chip-level power management. To accomplish these research objectives, analysis and simulation tools will be developed to characterize properties such as Ion/Ioff ratio, energy efficiency, and variation tolerance of the deeply-scaled (e.g., sub-10nm) FinFET devices. In addition, questions of how the new devices can be used for designing memory and logic cells that can seamlessly operate at low (near-threshold) and high (super-threshold) supply voltages will be explored. Finally, key challenges in modeling, deployment, and reconfiguration of circuit fabrics and architectural templates to improve the overall energy efficiency of system-on-chip designs will be addressed.

最近的研究强调了节能计算对维持​​信息技术进步并应对关键社会挑战的重要性。探索整体功率优化和管理解决方案，这些解决方案跨越了该项目中要研究的计算堆栈和基础架构的多层层面，将更好地启用可用的机会，以最大程度地提高能源效率。这项研究将推进以下设备设计，建模和优化，标准电池库的设计和表征，电路速度与能源效率与可靠性贸易贸易空间探索以及芯片级别的异质性建模的最先进。这项研究的挑战和机遇将为开发许多技术和方法设计未来的节能计算系统所需的技术和方法，并确保信息技术生态系统的可持续性。该项目增强的教育，外展和培训计划将包括开发新的教育模块，招募少数人和代表性不足的学生，以及本科生的本科学习和研究实习机会。从技术的角度来看，该项目将在两个跨层次范围内进行创新：（I）技术和环境和（ii）技术和环境和（II）和（II）和（II）和（II）和（II）和（II）和（II）和（II）和Architecture。更确切地说，研究的第一障碍将着重于开发深入（多门）CMOS设备和逻辑细胞库，这些设备可提供高能量效率，快速开关速度和可靠性。第二个推力是针对低动态和备用电路的设计，能够在多个电压机制中具有稳健和能量的最佳操作的电路设计，以及用于有效芯片级功率管理的手段。为了实现这些研究目标，将开发分析和仿真工具，以表征诸如离子/IOFF比，能源效率和变化耐受性（例如，低于10nm）的鳍片设备等属性。此外，还将探索如何将新设备用于设计内存和逻辑单元的问题，这些记忆和逻辑单元将在低（接近阈值）和高（超阈值）电压电压下无缝操作。最后，将解决对电路织物和建筑模板的建模，部署和重新配置方面的关键挑战，以提高芯片芯片设计的整体能源效率。