Salphasic Clock Planes for Synchronous Systems on Printed Circuit Boards

用于印刷电路板上同步系统的 Salphasic 时钟平面

• 批准号: 9208904
• 负责人: Leandra Vicci
• 金额: $ 9.51万
• 依托单位: University of North Carolina at Chapel Hill
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 1992
• 资助国家: 美国
• 起止时间: 1992-08-01 至 1995-07-31
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=9208904&HistoricalAwards=false
• 关键词: Salphasic; Clock; Planes; Synchronous; Systems

The design of globally synchronous systems must account for clock skew due to propagation delays through a distribution network. In large or fast systems, electrical path delays must be individually equalized, a tedious and error-prone process. Alternatively, systems can be designed in an asynchronous or clockless form, but asynchronous design is not currently or widely understood or practiced. Therefore, improved technology for distribution of clock signals continues to be important for high-performance systems. Sinusoidal clock signals in the form of standing waves on the clock-distribution conductors can substantially eliminate clock skew across a system. This has been operationally demonstrated in a branching tree of transmission lines in the Pixel-Planes 5 system, where a 160 MHz clock is distributed across a three-rack system with less than 200 ps skew. The work in this project will allow generalization to surfaces, suggesting the design of synchronous PC boards using clock planes for low-complexity and low-skew clock distribution. A series of experiments and circuit developments are being performed to reduce the clock-plane concept to engineering practice. The expected results of this research effort consist of a design methodology that is both simple and reliable, supported by a library of basic circuits and CAD tools.

由于通过分布网络的传播延迟，全球同步系统的设计必须解释时钟偏斜。 在大型或快速的系统中，必须单独均衡电路延迟，这是一个乏味且容易出错的过程。 另外，系统可以以异步或无钟形式设计，但是目前尚未或广泛理解或练习异步设计。 因此，改进的时钟信号分布技术对于高性能系统仍然很重要。 正弦时钟信号以时钟分布导体上的站立波的形式形式，可以大大消除整个系统的时钟偏斜。 这已在像素平面5系统的传输线的分支树中进行操作，其中160 MHz时钟分布在少于200 ps偏斜的三座系统上。 该项目中的工作将使概括到表面，并建议使用时钟平面进行低复杂性和低调时钟分布的同步PC板设计。 正在进行一系列实验和电路开发，以将时钟平面概念减少到工程实践。 这项研究工作的预期结果由一种设计方法组成，该方法既简单又可靠，并由基本电路和CAD工具的库支持。