Salphasic Clock Planes for Synchronous Systems on Printed Circuit Boards

用于印刷电路板上同步系统的 Salphasic 时钟平面

• 批准号: 9208904
• 负责人: Leandra Vicci
• 金额: $ 9.51万
• 依托单位: University of North Carolina at Chapel Hill
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 1992
• 资助国家: 美国
• 起止时间: 1992-08-01 至 1995-07-31
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=9208904&HistoricalAwards=false
• 关键词: Salphasic; Clock; Planes; Synchronous; Systems

The design of globally synchronous systems must account for clock skew due to propagation delays through a distribution network. In large or fast systems, electrical path delays must be individually equalized, a tedious and error-prone process. Alternatively, systems can be designed in an asynchronous or clockless form, but asynchronous design is not currently or widely understood or practiced. Therefore, improved technology for distribution of clock signals continues to be important for high-performance systems. Sinusoidal clock signals in the form of standing waves on the clock-distribution conductors can substantially eliminate clock skew across a system. This has been operationally demonstrated in a branching tree of transmission lines in the Pixel-Planes 5 system, where a 160 MHz clock is distributed across a three-rack system with less than 200 ps skew. The work in this project will allow generalization to surfaces, suggesting the design of synchronous PC boards using clock planes for low-complexity and low-skew clock distribution. A series of experiments and circuit developments are being performed to reduce the clock-plane concept to engineering practice. The expected results of this research effort consist of a design methodology that is both simple and reliable, supported by a library of basic circuits and CAD tools.

全局同步系统的设计必须考虑由于通过分发网络的传播延迟而导致的时钟偏差。 在大型或快速系统中，必须单独均衡电气路径延迟，这是一个繁琐且容易出错的过程。 或者，系统可以以异步或无时钟形式设计，但异步设计目前尚未广泛理解或实践。 因此，改进时钟信号分配技术对于高性能系统仍然很重要。 时钟分配导体上驻波形式的正弦时钟信号可以基本上消除系统中的时钟偏差。 这已在 Pixel-Planes 5 系统中的传输线分支树中得到了实际证明，其中 160 MHz 时钟分布在三机架系统上，偏差小于 200 ps。 该项目的工作将允许推广到表面，建议使用时钟平面来设计同步 PC 板，以实现低复杂性和低偏斜时钟分布。 正在进行一系列实验和电路开发，以将时钟平面概念简化为工程实践。 这项研究工作的预期结果包括一种既简单又可靠的设计方法，并得到基本电路和 CAD 工具库的支持。