支持片上学习的大规模脉冲神经网络芯片关键技术研究

Spiking Neural Network (SNN) based hardware is a research direction to approach brains computational and power efficiency. Existing hardware implementation of SNN are limited in scale or do not have in-hardware learning capability. We propose a scalable Network-on-chip based SNN hardware architecture with in-hardware STDP learning capability. First, a neuron cluster with hierarchical power management is proposed as the basic communication node for NoC. For the tradeoff between neural network accuracy and hardware resource, both linear and non-linear quantization method is proposed for the synaptic weight. Second, for the scalability of the SNN, dynamic zero reference and relative addressing method are adopted to overcome the limitation of the address width. What’s more, the spike traffic compression and re-order techniques are incorporated to reduce the traffic overhead and improve the throughput on the network. At last, an efficient STDP micro-architecture is proposed for in-hardware online learning. It utilizes the spike window and spike feed-back techniques to overcome the spatial and temporal gab between pre-synaptic neuron and post-synaptic neuron in SNN hardware.

脉冲神经网络具有高度的生物真实性，其高能效比的优势使其成为类脑计算芯片的研究热点。但目前的脉冲神经网络芯片均不支持在线学习且神经元规模扩展性受到限制，本项目拟提出一种基于片上网络的在线自学习大规模脉冲神经网络架构，该架构以支持层次化功耗管理的神经元簇为通信节点，支持突触权重的低精度线性和高精度非线性量化，实现神经网络精度与存储资源的平衡，片上网络以动态参考原点和相对寻址方式索引目标神经元，使神经元间互连距离和扩展性不受地址位宽约束；最后，提出了基于脉冲序列窗口和脉冲反向传播技术的STDP学习规则，分别解决了传统STDP学习规则时间窗口内脉冲数量无法确定和前后突触脉冲的空间跨度大的问题。

本项目提出了一种基于片上网络的在线自学习大规模脉冲神经网络架构，该架构采用全局异步局部同步的通信方式，提升架构的高度可扩张性同时保证了局部的脉冲事件处理性能。采用基于事件驱动工作机理和层次化功耗管理机制，保证无脉冲事件驱动的神经元处于休眠状态，实现芯片的极低级功耗，并自主定义了一套高稳定性的芯片间神经脉冲事件异步通信协议，支持多片芯片的级联，支持用户构建千万级神经元类脑计算系统。此外，片上网络以动态参考原点和相对寻址方式索引目标神经元，使神经元间互连距离和扩展性不受地址位宽约束，并结合神经脉冲事件的重排序和压缩技术，减少数据传输带宽，提高脉冲时间传输的实时性；提出了基于存储共享的突触架构，支持突触权重的低精度线性和高精度非线性量化，实现神经网络精度与存储资源的平衡。最后，提出了基于脉冲序列窗口和脉冲反向传播技术的STDP学习规则，分别解决了传统STDP学习规则时间窗口内脉冲数量无法确定和前后突触脉冲的空间跨度大的问题。

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